66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
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Table 7-21. MPU12-MPU15 Programmable Range n Memory Protection Page Attribute Register
(PROGn_MPPAR) Reset Values (continued)
REGISTER MPU12 MPU13 MPU14 MPU15
PROG15_MPPAR N/A N/A N/A N/A
7.3 Interrupts for 66AK2E0x
This section discusses the interrupt sources, controller, and topology. Also provided are tables describing
the interrupt events.
7.3.1 Interrupt Sources and Interrupt Controller
The ARM CorePac interrupts on the 66AK2E0x device are configured through the ARM CorePac Interrupt
Controller. It allows for up to 480 system events to be programmed to any of the ARM core’s IRQ/FIQ
interrupts. In addition error-class events or infrequently used events are also routed through the system
event router to offload the ARM CorePac interrupt controller. This is accomplished through the CorePac
Interrupt Controller block CIC2. Further, CIC2 provides 8 events each to EDMA3CC0, EDMA3CC1,
EDMA3C2, EDMA3CC3, EDMA3CC4, and Hyperlink.
The DSP CorePac interrupts on the 66AK2E0x device are configured through the C66x CorePac Interrupt
Controller. The Interrupt Controller allows for up to 128 system events to be programmed to any of the 12
CPU interrupt inputs (CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced
emulation logic. The 128 system events consist of both internally-generated events (within the CorePac)
and chip-level events. In addition, error-class events or infrequently used events are also routed through
the system event router to offload the C66x CorePac interrupt selector. This is accomplished through the
CorePac Interuupt Controller blocks, CIC2 and CIC0. This is clocked using CPU/6.
Modules such as CP_MPU, BOOT_CFG, and CP_Tracer have level interrupts and EOI handshaking
interface. The EOI value is 0 for CP_MPU, BOOT_CFG, and CP_Tracer.
Figure 7-4 shows the 66AK2E0x interrupt topology.
84 Memory, Interrupts, and EDMA for 66AK2E0x Copyright © 2012–2015, Texas Instruments Incorporated
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