Packet
DMA
Multicore Navigator
Queue
Manager
Debug & Trace
Semaphore
HyperLink
TeraNet
1 C66x DSP Core and 1 ARM Core
@ up to 1.4 GHz
Boot ROM
Power
Management
4MB L2 Cache
32KB L1
P-Cache
32KB L1
D-Cache
ARM
A15
MSMC
2MB
MSM
SRAM
72-Bit
DDR3 EMIF
Memory Subsystem
Secure Mode
3´
PLL
5´
EDMA
66AK2E02
C66x™
CorePac
512KB L2 Cache
32KB L1
P-Cache
32KB L1
D-Cache
Network Coprocessor
9-Port
Ethernet
Switch
Packet
Accelerator
Security
Accelerator
1GBE
1GBE
1GBE
1GBE
1GBE
1GBE
1GBE
1GBE
3´ SPI
3´ I C
2
2´ USB 3.0
2´ UART
GPIO 32´
2 PCIe 2´ ´
EMIF16
TSIP
USIM
66AK2E05, 66AK2E02
www.ti.com
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Figure 1-2. 66AK2E02 Functional Block Diagram
Table of Contents
1 66AK2E0x Features and Description ................ 1 3 Device Characteristics.................................. 8
1.1 Features .............................................. 1 3.1 C66x DSP CorePac .................................. 9
1.2 Applications........................................... 2 3.2 ARM CorePac ........................................ 9
1.3 KeyStone II Architecture.............................. 2 3.3 Development Tools.................................. 10
1.4 Device Description ................................... 2 3.4 Device Nomenclature ............................... 10
1.5 Enhancements in KeyStone II........................ 3 3.5 Related Documentation from Texas Instruments ... 12
1.6 Functional Block Diagram ............................ 4 3.6 Related Links........................................ 13
2 Revision History ......................................... 7 3.7 Community Resources .............................. 13
Copyright © 2012–2015, Texas Instruments Incorporated Table of Contents 5
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Product Folder Links: 66AK2E05 66AK2E02