66AK2E05, 66AK2E02
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 6-2. Terminal Functions — Signals and Control by Function (continued)
SIGNAL NAME BALL NO. TYPE IPD/IPU DESCRIPTION
Y33 I Down Post divider select for main PLL.. Secondary function for GPIO14.
MAINPLLODSEL
2
Clock / Reset
CORECLKN AG1 I
System clock input to main PLL
CORECLKP AF1 I
DDRCLKN G3 I
DDR3 reference clock input to DDR PLL
DDRCLKP G4 I
HOUT AF30 OZ Up Interrupt output pulse created by IPCGRH
HYPLNK0CLKN AJ8 I
HyperLink reference clock to drive HyperLink SerDes
HYPLNK0CLKP AJ7 I
LRESETNMIEN AE30 I Up Enable for DSP core
LRESET AF33 I Up Warm reset
NETCPCLKN AN3 I
NETCP sub-system reference clock
NETCPCLKP AM2 I
NETCPCLKSEL AG6 I Down NETCP clock select to choose between core clock and NETCPCLK pins
NMI AG33 I Up Non-maskable interrupt
PCIE0CLKN AJ18 I
PCIe Clock input to drive PCIe0 SerDes
PCIE0CLKP AJ17 I
PCIE1CLKN AJ15 I
PCIe Clock Input to drive PCIe1 SerDes
PCIE1CLKP AJ14 I
POR AH33 I Power-on reset
RESETFULL AF32 I Up Full reset
RESETSTAT AH29 O Up Reset Status Output. Drives low during Power-on Reset (No HHV override). Available after core
and IOs are completely powered-up.
RESET AE29 I Up Warm reset of non-isolated portion of the device
SGMII0CLKN AJ25 I
SGMII reference clock to drive both SGMII0 SerDes SGMII reference clock to drive the SGMII
SerDes
SGMII0CLKP AJ24 I
SYSCLKOUT AE4 OZ Down System clock output to be used as a general purpose output clock for debug purposes
TSREFCLKN AK1 I
Clock from external OCXO/VCXO for SyncE
TSREFCLKP AK2 I
TSRXCLKOUT0N AJ2 O
SERDES recovered clock output for SyncE
TSRXCLKOUT0P AJ1 O
TSRXCLKOUT1N AH1 O
SERDES recovered clock output for SyncE
TSRXCLKOUT1P AG2 O
USBCLKM T4 I
USB0_3.0 reference clock
USBCLKP U4 I
XFICLKN AJ12 I
XFI reference clock to drive the XFI SerDes
XFICLKP AJ11 I
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