66AK2E05, 66AK2E02
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
TI's C66x core launches a new era of DSP technology by combining fixed-point and floating point
computational capability in the processor without sacrificing speed, size, or power consumption. The raw
computational performance is an industry-leading 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz
operating frequency). It can execute 8 single precision floating point MAC operations per cycle and can
perform double- and mixed-precision operations and is IEEE754 compliant. For fixed-point use, the C66x
core has 4× the multiply accumulate (MAC) capability of C64x+ cores. The C66x CorePac incorporates 90
new instructions targeted for floating point and vector math oriented processing. These enhancements
yield sizeable performance improvements in popular DSP kernels used in signal processing,
mathematical, and image acquisition functions. The C66x core is backwards code compatible with TI's
previous generation C6000 fixed and floating point DSP cores, ensuring software portability and shortened
software development cycles for applications migrating to faster hardware.
The 66AK2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15
processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15
cores in the ARM CorePac share a 4MB L2 Cache. In the DSP CorePac, in addition to 32KB of L1
program and 32KB of L1 data cache, there is 512KB of dedicated memory per core that can be configured
as cache or as memory mapped RAM. The device also integrates 2MB of Multicore Shared Memory
(MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection
and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with
ECC support) external memory interface (EMIF) running at 1600 MTPS.
The device enables developers to use a variety of development and debugging tools that include GNU
GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space
debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.
1.5 Enhancements in KeyStone II
The KeyStone II architecture provides many major enhancements over the previous KeyStone I
generation of devices. The KeyStone II architecture integrates an ARM Cortex-A15 processor quad-core
cluster to enable Layer 2 (MAC/RLC) and higher layer processing. The number of DSP cores has been
doubled for 2× improvement in Layer 1 processing. The external memory bandwidth has been doubled
with the integration of dual DDR3 1600 EMIFs. MSMC internal memory bandwidth is quadrupled with
MSMC V2 architecture improvements. Multicore Navigator supports 2× the number of queues, descriptors
and packet DMA, 4× the number of micro RISC engines and a significant increase in the number of
push/pops per second, compared to the previous generation. The new peripherals that have been added
include the USB 3.0 controller and Asynchronous EMIF controller for NAND/NOR memory access. The 2-
port Gigabit Ethernet switch in KeyStone I has been replaced with an 8-port Gigabit Ethernet switch and a
10 GbE switch in KeyStone II. Time synchronization support has been enhanced to reduce software
workload and support additional standards like IEEE1588 Annex D/E and SyncE. The number of GPIOs
and serial interface peripherals like I
2
C and SPI have been increased to enable more board level control
functionality.
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