66AK2E05, 66AK2E02
www.ti.com
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 11-63. Peripherals Emulation Support (continued)
EMULATION SUSPEND SUPPORT EMULATION
REQUEST DEBUG
STOP- REAL-TIME SUPPORT PERIPHERAL
PERIPHERAL MODE MODE FREE BIT STOP BIT (cemudbg/emudbg) ASSIGNMENT
10GbE (ethernet Y N Y Y N 29
switch)
(1)
USBSS N N N N N NA
(1) 10 GbE supported by 66AK2E05only.
Based on the above table the number of suspend interfaces in Keystone II devices is listed below.
Table 11-64. EMUSUSP Peripheral Summary (for EMUSUSP handshake from DEBUGSS)
INTERFACES NUM_SUSPEND_PERIPHERALS
EMUSUSP Interfaces 54
EMUSUSP Realtime Interfaces 15
Table 11-65 summarizes the DEBUG core assignment. Emulation suspend output of all the cores are
synchronized to SYSCLK1/6 which is frequency of the slowest peripheral that uses these signals.
Table 11-65. EMUSUSP Core Summary(for EMUSUSP handshake to DEBUGSS)
Core # Assignment
0 C66x CorePac0
8..11 ARM CorePac0-3
12..29 Reserved
30 Logical OR of Core #0..11
31 Logical AND of Core #0..11
11.28.5 Advanced Event Triggering (AET)
The device supports advanced event triggering (AET). This capability can be used to debug complex
problems as well as understand performance characteristics of user applications. AET provides the
following capabilities:
• Hardware program breakpoints: specify addresses or address ranges that can generate events such
as halting the processor or triggering the trace capture.
• Data watchpoints: specify data variable addresses, address ranges, or data values that can generate
events such as halting the processor or triggering the trace capture.
• Counters: count the occurrence of an event or cycles for performance monitoring.
• State sequencing: allows combinations of hardware program breakpoints and data watchpoints to
precisely generate events for complex sequences.
Copyright © 2012–2015, Texas Instruments Incorporated 66AK2E0x Peripheral Information and Electrical Specifications 275
Submit Documentation Feedback
Product Folder Links: 66AK2E05 66AK2E02