66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
www.ti.com
11.28.4 Peripherals-Related Debug Requirement
Table 11-63 lists all the peripherals on this device, and the status of whether or not it supports emulation
suspend or emulation request events.
The DEBUGSS supports upto 32 debug suspend sources (processor cores) and 64 debug suspend sinks
(peripherals). The assignment of processor cores is shown in and the assignment of peripherals is shown
in Table 11-63. By default the logical AND of all the processor cores is routed to the peripherals. It is
possible to select an individual core to be routed to the peripheral (For example: used in tightly coupled
peripherals like timers), a logical AND of all cores (Global peripherals) or a logical OR of all cores by
programming the DEBUGSS.DRM module.
The SOFT bit should be programmed based on whether or not an immediate pause of the peripheral
function is required or if the peripheral suspend should occur only after a particular completion point is
reached in the normal peripheral operation. The FREE bit should be programmed to enable or disable the
emulation suspend functionality.
Table 11-63. Peripherals Emulation Support
EMULATION SUSPEND SUPPORT EMULATION
REQUEST DEBUG
STOP- REAL-TIME SUPPORT PERIPHERAL
PERIPHERAL MODE MODE FREE BIT STOP BIT (cemudbg/emudbg) ASSIGNMENT
Infrastructure Peripherals
EDMA_x, where N N N N Y NA
X=0/1/2/3/4
QM_SS Y (CPDMA Y (CPDMA Y (CPDMA Y (CPDMA Y 20
only) only) only) only)
CP_Tracers_X, where X = N N N N N NA
0..32
MPU_X, where X = 0..11 N N N N Y NA
CP_INTC N N N N Y NA
BOOT_CFG N N N N Y NA
SEC_MGR N N N N Y NA
PSC N N N N N NA
PLL N N N N N NA
TIMERx, x=0, 1..7, 8..19 Y N Y Y N 0, 1..7, 8..19
Semaphore N N N N Y NA
GPIO N N N N N NA
Memory Controller Peripherals
DDR3 N N N N Y NA
MSMC N N N N Y NA
EMIF16 N N N N Y NA
Serial Interfaces
I
2
C_X, where X = 0/1/2 Y N Y Y Y 21/22/23
SPI_X, where X = 0/1/2 N N N N Y NA
UART_X, where X = 0/1 Y N Y Y Y 24/25
USIM Y N Y N N 28
High Speed Serial Interfaces
Hyperlink N N N N Y
PCIeSS 0..1 N N N N N
Reserved 26
NetCP (ethernet switch) Y Y Y Y N 27
274 66AK2E0x Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: 66AK2E05 66AK2E02