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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 11-60. MSTID Mapping for Software Messages (continued)
CORE NAME MSTID [7:0] DESCRIPTION
Reserved 0x6
Reserved 0x7
A15 Core0 0x8 ARM Master IDs
A15 Core1 0x9 ARM Master ID (66AK2E05 only)
A15 Core2 0xA ARM Master ID(66AK2E05 only)
A15 Core3 0xB ARM Master ID(66AK2E05 only)
QMSS PDSPs 0x46 All QMSS PDSPs share the same master ID. Differentiating between the 8 PDSPs is done
through the channel number used
TSIP 0x80 TSIP Master ID
11.28.3 SoC Cross-Triggering Connection
The cross-trigger lines are shared by all the subsystems implementing cross-triggering. An MPU
subsystem trigger event can therefore be propagated to any application subsystem or system trace
component. The remote subsystem or system trace component can be programmed to be sensitive to the
global SOC trigger lines to either:
• Generate a processor debug request
• Generate an interrupt request
• Start/Stop processor trace
• Start/Stop CBA transaction tracing through CPTracers
• Start external logic analyzer trace
• Stop external logic analyzer trace
Table 11-61. Cross-Triggering Connection
SOURCE SINK
NAME TRIGGERS TRIGGERS COMMENTS
Inside DEBUGSS
Device-to-device trigger via EMU0/1 pins YES YES This is fixed (not affected by configuration)
MIPI-STM NO YES Trigger input only for MIPI-STM in DebugSS
CT-TBR YES YES DEBUGSS CT-TBR
CS-TPIU NO YES DEBUGSS CS-TPIU
Outside DEBUGSS
DSPSS YES YES
CP_Tracers YES YES
ARM YES YES ARM Cores, ARM CS-STM and ARM CT-
TBR
The following table describes the crosstrigger connection between various cross trigger sources and TI
XTRIG module.
Table 11-62. TI XTRIG Assignment
NAME ASSIGNED XTRIG CHANNEL NUMBER
C66x CorePac0 XTRIG 0
CPTracer 0..31 (The CPTracer number refers to the SID[4:0] as shown in XTRIG 8 .. 39
Table 11-59
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