66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
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11.28.1 Concurrent Use of Debug Port
The following combinations are possible concurrently:
• Trigger 0/1
• Trigger 0/1 and STM Trace (up to 4 data pins)
• Trigger 0/1 and STM Trace (up to 4 data pins) and C66x Trace (up to 20 data pins)
• Trigger 0/1 and STM Trace (1-4 data pins) and ARM Trace (27-24 data pins)
• STM Trace (1-4 data pins) and ARM Trace (29-26 data pins)
• Trigger 0/1 and ARM Trace (up to 29 data pins)
• ARM Trace (up to 32 data pins)
ARM and DSP simultaneous trace is not supported.
11.28.2 Master ID for HW and SW Messages
Table 11-59 describes the master ID for the various hardware and software masters of the STM.
Table 11-59. MSTID Mapping for Hardware Instrumentation (CPTRACERS)
CLOCK
CPTRACER NAME MSTID [7:0] DOMAIN SID[4:0] DESCRIPTION
CPT_MSMCx_MST, where x = 0x94-0x97 SYSCLK1/1 0x0..3 MSMC SRAM Bank 0 to MSMC SRAM Bank 3 monitors
0..3
CPT_MSMC4_MST 0xB1 SYSCLK1/1 0x4 MSMC SRAM Bank 4
CPT_MSMCx_MST, where x = 0xAE - 0xB0 SYSCLK1/1 0x5..7 MSMC SRAM Bank 5to MSMC SRAM Bank 7 monitors
5..7
CPT_DDR3_MST 0x98 SYSCLK1/1 0x8 MSMC DDR3 port monitor
CPT_L2_x_MST, where x = 0..7 0x8C - 0x93 SYSCLK1/3 0x9..0x10 DSP 0 to 7 SDMA port monitors
CPT_TPCC0_4_MST 0xA4 SYSCLK1/3 0x11 EDMA 0 and EDMA 4 CFG port monitor
CPT_TPCC1_2_3_MST 0xA5 SYSCLK1/3 0x12 EDMA 1, EDMA2 and EDMA3 CFG port monitor
CPT_INTC_MST 0xA6 SYSCLK1/3 0x13 INTC port monitor (for INTC 0/1/2 and GIC400)
CPT_SM_MST 0x99 SYSCLK1/3 0x14 Semaphore CFG port monitors
CPT_QM_CFG1_MST 0x9A SYSCLK1/3 0x15 QMSS CFG1 port monitor
CPT_QM_CFG2_MST 0xA0 SYSCLK1/3 0x16 QMSS CFG2 port monitor
CPT_QM_M_MST 0x9B SYSCLK1/3 0x17 QM_M CFG/DMA port monitor
CPT_SPI_ROM_EMIF16_MST 0xA7 SYSCLK1/3 0x18 SPI ROM EMIF16 CFG port monitor
CPT_CFG_MST 0x9C SYSCLK1/3 0x19 SCR_3P_B and SCR_6P_B CFG peripheral port
monitors
Reserved 0x1A Reserved
Reserved 0x1B Reserved
Reserved 0x1C Reserved
Reserved 0x1D Reserved
Reserved 0x1E Reserved
Reserved 0x1F DDR 3B port monitor (on SCR 3C)
Table 11-60. MSTID Mapping for Software Messages
CORE NAME MSTID [7:0] DESCRIPTION
C66x CorePac0 0x0 C66x CorePac MDMA Master ID
Reserved 0x1
Reserved 0x2
Reserved 0x3
Reserved 0x4
Reserved 0x5
272 66AK2E0x Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated
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