6
8
4
7
9
5
10
12
13
3
EM_CE[3:0]
EM_R/W
EM_BA[1:0]
EM_A[21:0]
EM_OE
EM_D[15:0]
EM_WE
66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
www.ti.com
Table 11-57. EMIF16 Asynchronous Memory Timing Requirements
(1)
(continued)
(see Figure 11-52 through Figure 11-55)
NO. MIN MAX UNIT
7 t
oh
(OEH-BAIV) Output hold time from OE high to BA invalid (RH+1) * E - 3 (RH+1) * E + 3 ns
8 t
osu
(AV-OEL) Output setup time from A valid to OE low (RS+1) * E - 3 (RS+1) * E + 3 ns
9 t
oh
(OEH-AIV) Output hold time from OE high to A invalid (RH+1) * E - 3 (RH+1) * E + 3 ns
10 t
w
(OEL) OE active time low, when ew = 0. Extended wait mode is disabled. (RST+1) * E - 3 (RST+1) * E + 3 ns
10 t
w
(OEL) OE active time low, when ew = 1. Extended wait mode is enabled. (RST+1) * E - 3 (RST+1) * E + 3 ns
11 t
d
(WAITH-OEH) Delay time from WAIT deasserted to OE# high 4E + 3 ns
12 t
su
(D-OEH) Input setup time from D valid to OE high 3 ns
13 t
h
(OEH-D) Input hold time from OE high to D invalid 0.5 ns
Write Timing
15 EMIF write cycle time when ew = 0, meaning not in extended wait (WS+WST+WH+ (WS+WST+WH+ ns
t
c
(CEL)
mode 3)*E-3 3)*E+3
15 EMIF write cycle time when ew =1., meaning extended wait mode is (WS+WST+WH+ (WS+WST+WH+ ns
t
c
(CEL)
enabled 3)*E-3 3)*E+3
16 Output setup time from CE low to WE low. SS = 0, not in select strobe ns
t
osu
CEL-WEL) (WS+1) * E - 3
mode
17 Output hold time from WE high to CE high. SS = 0, not in select strobe ns
t
oh
(WEH-CEH) (WH+1) * E - 3
mode
16 Output setup time from CE low to WE low in select strobe mode, SS = ns
t
osu
CEL-WEL) (WS+1) * E - 3
1
17 Output hold time from WE high to CE high in select strobe mode, SS = ns
t
oh
(WEH-CEH) (WH+1) * E - 3
1
18 t
osu
(RNW-WEL) Output setup time from RNW valid to WE low (WS+1) * E - 3 ns
19 t
oh
(WEH-RNW) Output hold time from WE high to RNW invalid (WH+1) * E - 3 ns
20 t
osu
(BAV-WEL) Output setup time from BA valid to WE low (WS+1) * E - 3 ns
21 t
oh
(WEH-BAIV) Output hold time from WE high to BA invalid (WH+1) * E - 3 ns
22 t
osu
(AV-WEL) Output setup time from A valid to WE low (WS+1) * E - 3 ns
23 t
oh
(WEH-AIV) Output hold time from WE high to A invalid (WH+1) * E - 3 ns
24 t
w
(WEL) WE active time low, when ew = 0. Extended wait mode is disabled. (WST+1) * E - 3 ns
24 t
w
(WEL) WE active time low, when ew = 1. Extended wait mode is enabled. (WST+1) * E - 3 ns
26 t
osu
(DV-WEL) Output setup time from D valid to WE low (WS+1) * E - 3 ns
27 t
oh
(WEH-DIV) Output hold time from WE high to D invalid (WH+1) * E - 3 ns
25 t
d
(WAITH-WEH) Delay time from WAIT deasserted to WE# high 4E + 3 ns
Figure 11-52. EMIF16 Asynchronous Memory Read Timing Diagram
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