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66AK2E05XABD4

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型号: 66AK2E05XABD4
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功能描述: 66AK2E0x Multicore DSPARM KeyStone II System-on-Chip (SoC)
PDF文件大小: 1546.9 Kbytes
PDF页数: 共282页
制造商: TI[Texas Instruments]
制造商LOGO: TI[Texas Instruments] LOGO
制造商网址: http://www.ti.com
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120%
ts127-2ts127-3 ts127-0ts127-1 ts000-7 ts000-6 ts000-1ts000-3ts000-5 ts000-4 ts000-2 ts000-0
ts000-3ts127-2ts127-3 ts000-7ts127-1 ts127-0 ts000-5ts000-6 ts000-4 ts000-0ts000-2 ts000-1
11 12
13
15
16
18
17
19
CLKA/B
FSA/B
TR[n]
TX[n]
66AK2E05, 66AK2E02
www.ti.com
SPRS865D NOVEMBER 2012REVISED MARCH 2015
A. Example timeslot numbering shown is for 8.192 Mbps links; 16.384 Mbps links have timeslots numbered 0 through
255 and 32.768 Mbps links have timeslots numbered 0 through 511. The data timing shown relative to the clock and
frame sync signals would require a RCVDATD=1023 and a XMTDATD=1023.
Figure 11-51. TSIP 1x Timing Diagram
(A)
11.25 Universal Subscriber Identity Module (USIM)
The 66AK2E0x is equipped with a Universal Subscriber Identity Module (USIM) for user authentication.
The USIM is compatible with ISO, ETSI/GSM, and 3GPP standards.
The USIM is implemented for support of secure devices only. Contact your local technical sales
representative for further details.
11.26 EMIF16 Peripheral
The EMIF16 module provides an interface between the device and external memories such as NAND and
NOR flash. For more information, see the KeyStone Architecture External Memory Interface (EMIF16)
User's Guide (SPRUGZ3).
11.26.1 EMIF16 Electrical Data/Timing
Table 11-57. EMIF16 Asynchronous Memory Timing Requirements
(1)
(see Figure 11-52 through Figure 11-55)
NO. MIN MAX UNIT
General Timing
2 t
w
(WAIT) Pulse duration, WAIT assertion and deassertion minimum time 2E ns
28 t
d
(WAIT-WEH) Setup time, WAIT asserted before WE high 4E + 3 ns
14 t
d
(WAIT-OEH) Setup time, WAIT asserted before OE high 4E + 3 ns
Read Timing
3 EMIF read cycle time when ew = 0, meaning not in extended wait (RS+RST+RH+3) (RS+RST+RH+3) ns
t
C
(CEL)
mode *E-3 *E+3
3 EMIF read cycle time when ew =1, meaning extended wait mode (RS+RST+RH+3) (RS+RST+RH+3) ns
t
C
(CEL)
enabled *E-3 *E+3
4 Output setup time from CE low to OE low. SS = 0, not in select strobe ns
t
osu
(CEL-OEL) (RS+1) * E - 3 (RS+1) * E + 3
mode
5 Output hold time from OE high to CE high. SS = 0, not in select strobe ns
t
oh
(OEH-CEH) (RH+1) * E - 3 (RH+1) * E + 3
mode
4 Output setup time from CE low to OE low in select strobe mode, SS = ns
t
osu
(CEL-OEL) (RS+1) * E - 3 (RS+1) * E + 3
1
5 Output hold time from OE high to CE high in select strobe mode, SS = ns
t
oh
(OEH-CEH) (RH+1) * E - 3 (RH+1) * E + 3
1
6 t
osu
(BAV-OEL) Output setup time from BA valid to OE low (RS+1) * E - 3 (RS+1) * E + 3 ns
(1) E = 1/(SYSCLK1/6)
Copyright © 2012–2015, Texas Instruments Incorporated 66AK2E0x Peripheral Information and Electrical Specifications 265
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Product Folder Links: 66AK2E05 66AK2E02
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