66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
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11.19 Ten-Gigabit Ethernet (10GbE) Switch Subsystem
The 3-port Ten Gigabit Ethernet Switch Subsystem (different from the Network Coprocessor integrated
switch) includes a standalone EMAC switch subsystem and a 2-lane SerDes macro. The 2-lane macro
enables only 2 external ports. It does not include any packet acceleration or security acceleration engine.
11.19.1 10GbE Supported Features
The key features of the 10GbE module are listed below:
• 10 Gbps EMAC switch subsystem
– MDIO: Media-dependent input/output module
– SGMII Interface for 10/100/1000 and 10GBASE-KR for 10G
– Ethernet switch with wire-rate switching (only two external ports are supported by the SerDes)
– CPTS module that supports time-stamping for IEEE1588v2 with support for eight hardware push
events and generation of compare output pulses
– Supports XFI electrical interface
• CPDMA
The CPDMA component provides CPPI 4.2 compatible functionality, and provides a 128-bit wide data path
to the TeraNet, enabling:
• Support for 8 transmit channel and 16 receive channels
• Support for reset isolation option
For more information, see the KeyStone II Architecture 10 Gigabit Ethernet Subsystem User's Guide
(SPRUHJ5).
11.20 Timers
The timers can be used to time events, count events, generate pulses, interrupt the C66x CorePacs and
ARM CorePac and send synchronization events to the EDMA3 channel controller.
11.20.1 Timers Device-Specific Information
The 66AK2E0x device has up to twenty 64-bit timers in total, but only 13 timers are used in 66AK2E05
and 12 timers are used in 66AK2E02, of which Timer0 is dedicated to the C66x CorePacs Core 0 as
watchdog timers and can also be used as general-purpose timers. Timer16 and Timer17 (66AK2E02) or
Timer16 through Timer19 (66AK2E05) are dedicated to each of the Cortex-A15 processor cores as a
watchdog timer and can also be used as general-purpose timers. The Timer8 through Timer15 can be
configured as general-purpose timers only, with each timer programmed as a 64-bit timer or as two
separate 32-bit timers.
When operating in 64-bit mode, the timer counts either module clock cycles or input (TINPLx) pulses
(rising edge) and generates an output pulse/waveform (TOUTLx) plus an internal event (TINTLx) on a
software-programmable period. When operating in 32-bit mode, the timer is split into two independent 32-
bit timers. Each timer is made up of two 32-bit counters: a high counter and a low counter. The timer pins,
TINPLx and TOUTLx are connected to the low counter. The timer pins, TINPHx and TOUTHx are
connected to the high counter.
When operating in watchdog mode, the timer counts down to 0 and generates an event. It is a
requirement that software writes to the timer before the count expires, after which the count begins again.
If the count ever reaches 0, the timer event output is asserted. Reset initiated by a watchdog timer can be
set by programming the Reset Type Status Register (RSTYPE) (see Section 11.5.2.6) and the type of
reset initiated can set by programming the Reset Configuration Register (RSTCFG) (see
Section 11.5.2.8). For more information, see the KeyStone Architecture Timer 64P User's Guide
SPRUGV5.
260 66AK2E0x Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated
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