66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
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There is a central processor time synchronization (CPTS) submodule in the Ethernet switch module that
can be used for time synchronization. Programming this register selects the clock source for the
CPTS_RCLK. See the Gigabit Ethernet (GbE) Switch Subsystem (1 GB) User's Guide (SPRUGV9) for the
register address and other details about the time synchronization submodule. The register
CPTS_RFTCLK_SEL for reference clock selection of the time synchronization submodule is shown in
Figure 11-45.
CPTS also allows 8 HW signal inputs for timestamping. Two of these signals are connected to
TSPUSHEVT0 and TSPUSHEVT1. The other 6 are connected to internal SyncE and timer signals. See
Table 11-46 for interconnectivity. Regarding the SyncE signal, see Section 9.2.3.26 for more details on
how to control this input. Furthermore, see the Gigabit Ethernet (GbE) Switch Subsystem (1 GB) User's
Guide (SPRUGV9) for details on how to enable HW timestamping on CPTS.
Table 11-46. CPTS Hardware Push Events
EVENT NUMBER CONNECTION
1 syncE
2 XGE sync
3 Tspushevt1
4 Tspushevt0
5 Timi1
6 Timi0
7 Reserved
8 Reserved
Figure 11-45. RFTCLK Select Register (CPTS_RFTCLK_SEL)
31 4 3 0
Reserved CPTS_RFTCLK_SEL
R - 0 RW - 0
Legend: R = Read only; -x, value is indeterminate
Table 11-47. RFTCLK Select Register Field Descriptions
Bit Field Description
31-4 Reserved Reserved. Read as 0.
3-0 CPTS_RFTCLK_SE Reference clock select. This signal is used to control an external multiplexer that selects one of 8 clocks for
L time sync reference (RFTCLK). This CPTS_RFTCLK_SEL value can be written only when the CPTS_EN
bit is cleared to 0 in the TS_CTL register.
• 0000 = SYSCLK2
• 0001 = SYSCLK3
• 0010 = TIMI0
• 0011 = TIMI1
• 0100 = TSIPCLKA
• 1000 = TSREFCLK
• 1100 = TSIPCLKB
• Others = Reserved
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