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66AK2E05XABD4

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型号: 66AK2E05XABD4
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功能描述: 66AK2E0x Multicore DSPARM KeyStone II System-on-Chip (SoC)
PDF文件大小: 1546.9 Kbytes
PDF页数: 共282页
制造商: TI[Texas Instruments]
制造商LOGO: TI[Texas Instruments] LOGO
制造商网址: http://www.ti.com
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120%
7
RXD Bit N-1 Bit N Stop Start
CTS
32
2
1
Stop/Idle
TXD Start Bit 0
Bit 1 Bit N-1 Bit N Parity Stop Idle Start
66AK2E05, 66AK2E02
SPRS865D NOVEMBER 2012REVISED MARCH 2015
www.ti.com
Table 11-43. UART Switching Characteristics
(see Figure 11-41 and Figure 11-42)
NO. PARAMETER MIN MAX UNIT
Transmit Timing
1 tw(TXSTART) Pulse width, transmit start bit U
(1)
- 2 U + 2 ns
2 tw(TXH) Pulse width, transmit data/parity bit high U - 2 U + 2 ns
2 tw(TXL) Pulse width, transmit data/parity bit low U - 2 U + 2 ns
3 tw(TXSTOP1) Pulse width, transmit stop bit 1 U - 2 U + 2 ns
3 tw(TXSTOP15) Pulse width, transmit stop bit 1.5 1.5 * (U - 2) 1.5 * ('U + 2) ns
3 tw(TXSTOP2) Pulse width, transmit stop bit 2 2 * (U - 2) 2 * ('U + 2) ns
Autoflow Timing Requirements
7 td(RX-RTSH) Delay time, STOP bit received to RTS deasserted P
(2)
5P ns
(1) U = UART baud time = 1/programmed baud rate
(2) P = 1/(SYSCLK1/6)
Figure 11-41. UART Transmit Timing Waveform
Figure 11-42. UART RTS (Request-to-Send Output) Autoflow Timing Waveform
11.14 PCIe Peripheral
The two-lane PCI express (PCIe) module on 66AK2E0x provides an interface between the device and
other PCIe-compliant devices. The PCIe module provides low pin-count, high-reliability, and high-speed
data transfer at rates up to 5.0 Gbps per lane on the serial links. For more information, see the KeyStone
Architecture Peripheral Component Interconnect Express (PCIe) User's Guide (SPRUGS6).
11.15 Packet Accelerator
The Packet Accelerator (PA) provides L2 to L4 classification functionalities and supports classification for
Ethernet, VLAN, MPLS over Ethernet, IPv4/6, GRE over IP, and other session identification over IP such
as UDP ports. It maintains 8k multiple-in, multiple-out hardware queues and also provides checksum
capability as well as some QoS capabilities. The PA enables a single IP address to be used for a
multicore device and can process up to 1.5 Mpps. The Packet Accelerator is coupled with the Network
Coprocessor. For more information, see the KeyStone II Architecture Packet Accelerator 2 (PA2) for K2E
and K2L Devices User's Guide (SPRUHZ2).
256 66AK2E0x Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated
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Product Folder Links: 66AK2E05 66AK2E02
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