25
23
19
18
22
27
20
21
17
18
28
Stop Start Repeated
Start
Stop
SDA
SCL
16
26
24
66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
www.ti.com
Figure 11-33. I
2
C Transmit Timings
11.11 SPI Peripheral
The Serial Peripheral Interconnect (SPI) module provides an interface between the SoC and other SPI-
compliant devices. The primary intent of this interface is to allow for connection to an SPI ROM for boot.
The SPI module on 66AK2E0x is supported only in master mode. Additional chip-level components can
also be included, such as temperature sensors or an I/O expander.
11.11.1 SPI Electrical Data/Timing
Table 11-38. SPI Timing Requirements
(see Figure 11-34)
NO. MIN MAX UNIT
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
7 tsu(SPIDIN-SPC) Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 0 2 ns
7 tsu(SPIDIN-SPC) Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 1 2 ns
7 tsu(SPIDIN-SPC) Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 0 2 ns
7 tsu(SPIDIN-SPC) Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 1 2 ns
8 th(SPC-SPIDIN) Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 0 5 ns
8 th(SPC-SPIDIN) Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 1 5 ns
8 th(SPC-SPIDIN) Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 0 5 ns
8 th(SPC-SPIDIN) Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 1 5 ns
Table 11-39. SPI Switching Characteristics
(see Figure 11-34 and Figure 11-35)
NO. PARAMETER MIN MAX UNIT
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
1 tc(SPC) Cycle time, SPICLK, all master modes 3*P2
(1)
ns
2 tw(SPCH) Pulse width high, SPICLK, all master modes 0.5*(3*P2) - 1 ns
3 tw(SPCL) Pulse width low, SPICLK, all master modes 0.5*(3*P2) - 1 ns
4 td(SPIDOUT-SPC) Setup (Delay), initial data bit valid on SPIDOUT to initial edge ns
5
on SPICLK. Polarity = 0, Phase = 0.
4 td(SPIDOUT-SPC) Setup (Delay), initial data bit valid on SPIDOUT to initial edge ns
5
on SPICLK. Polarity = 0, Phase = 1.
4 td(SPIDOUT-SPC) Setup (Delay), initial data bit valid on SPIDOUT to initial edge ns
5
on SPICLK Polarity = 1, Phase = 0
(1) P2=1/(SYSCLK1/6)
250 66AK2E0x Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated
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