Cortex
A15
FIQ, IRQ,
Virtual FIQ,
Virtual IRQ
16 PPIs
Generic
Interrupt
Controller
400
Global
Time Base
Counter
64 Bits
Peripherals
CIC2
480 SPI
Interrupts
VBUSP2AXI
Bridge
ARM INTC
16 Software
Generated
Inputs
VBUSP Interface
CPU/6 Clock
GTB Counter Clock
Power On Reset
Cortex
A15
FIQ, IRQ,
Virtual FIQ,
Virtual IRQ
4 PPIs
Generic
Interrupt
Controller
400
Global
Time Base
Counter
64 Bits
Peripherals
CIC2
480 SPI
Interrupts
VBUSP2AXI
Bridge
ARM INTC
16 Software
Generated
Inputs
VBUSP Interface
CPU/6 Clock
GTB Counter Clock
Power On Reset
66AK2E05, 66AK2E02
www.ti.com
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Figure 5-3. ARM Interrupt Controller for One Cortex-A15 Processor Core
Figure 5-4. ARM Interrupt Controller for Four Cortex-A15 Processor Cores
5.3.4 Endianess
The ARM CorePac can operate in either little endian or big endian mode. When the ARM CorePac is in
little endian mode and the rest of the system is in big endian mode, the bridges in the ARM CorePac are
responsible for performing the endian conversion.
5.4 CFG Connection
The ARM CorePac has two slave ports. The 66AK2E0x masters cannot access the ARM CorePac internal
memory space.
1. Slave port 0 (TeraNet 3P_A) is a 32 bit wide port used for the ARM Trace module.
2. Slave port 1 (TeraNet 3P_B) is a 32 bit wide port used to access the rest of the system configuration.
5.5 Main TeraNet Connection
There is one master port coming out of the ARM CorePac. The master port is a 256 bit wide port for the
transactions going to the MSMC and DDR_EMIF data spaces.
Copyright © 2012–2015, Texas Instruments Incorporated ARM CorePac 25
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