10
8
4
3
7
12
5
6
14
2
3
13
Stop Start Repeated
Start
Stop
SDA
SCL
1
11
9
66AK2E05, 66AK2E02
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 11-36. I
2
C Timing Requirements
(1)
(continued)
(see Figure 11-32)
STANDARD MODE FAST MODE
NO. MIN MAX MIN MAX UNIT
13 t
su(SCLH-SDAH)
Setup time, SCL high before SDA high (for STOP condition) 4 0.6 µs
14 t
w(SP)
Pulse duration, spike (must be suppressed) 0 50 ns
C
b
(5)
Capacitive load for each bus line 400 400 pF
Figure 11-32. I
2
C Receive Timings
Table 11-37. I
2
C Switching Characteristics
(1)
(see Figure 11-33)
STANDARD
MODE FAST MODE
NO. PARAMETER MIN MAX MIN MAX UNIT
16 t
c(SCL)
Cycle time, SCL 10 2.5 µs
17 Setup time, SCL high to SDA low (for a repeated START
t
su(SCLH-SDAL)
4.7 0.6 µs
condition)
18 Hold time, SDA low after SCL low (for a START and a repeated
t
h(SDAL-SCLL)
4 0.6 µs
START condition)
19 t
w(SCLL)
Pulse duration, SCL low 4.7 1.3 µs
20 t
w(SCLH)
Pulse duration, SCL high 4 0.6 µs
21 t
d(SDAV-SDLH)
Delay time, SDA valid to SCL high 250 100 ns
22 t
v(SDLL-SDAV)
Valid time, SDA valid after SCL low (for I
2
C bus devices) 0 0 0.9 µs
23 Pulse duration, SDA high between STOP and START
t
w(SDAH)
4.7 1.3 µs
conditions
24 t
r(SDA)
Rise time, SDA 1000 20 + 0.1C
b
(1)
300 ns
25 t
r(SCL)
Rise time, SCL 1000 20 + 0.1C
b
(1)
300 ns
26 t
f(SDA)
Fall time, SDA 300 20 + 0.1C
b
(1)
300 ns
27 t
f(SCL)
Fall time, SCL 300 20 + 0.1C
b
(1)
300 ns
28 t
d(SCLH-SDAH)
Delay time, SCL high to SDA high (for STOP condition) 4 0.6 µs
C
p
Capacitance for each I
2
C pin 10 10 pF
(1) C
b
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
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