66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
www.ti.com
11.10.2 I
2
C Peripheral Register Description
Table 11-35. I
2
C Registers
HEX ADDRESS OFFSETS ACRONYM REGISTER NAME
0x0000 ICOAR I
2
C Own Address Register
0x0004 ICIMR I
2
C Interrupt Mask/status Register
0x0008 ICSTR I
2
C Interrupt Status Register
0x000C ICCLKL I
2
C Clock Low-time Divider Register
0x0010 ICCLKH I
2
C Clock High-time Divider Register
0x0014 ICCNT I
2
C Data Count Register
0x0018 ICDRR I
2
C Data Receive Register
0x001C ICSAR I
2
C Slave Address Register
0x0020 ICDXR I
2
C Data Transmit Register
0x0024 ICMDR I
2
C Mode Register
0x0028 ICIVR I
2
C Interrupt Vector Register
0x002C ICEMDR I
2
C Extended Mode Register
0x0030 ICPSC I
2
C Prescaler Register
0x0034 ICPID1 I
2
C Peripheral Identification Register 1 [value: 0x0000 0105]
0x0038 ICPID2 I
2
C Peripheral Identification Register 2 [value: 0x0000 0005]
0x003C -0x007F - Reserved
11.10.3 I
2
C Electrical Data/Timing
11.10.3.1 Inter-Integrated Circuits (I
2
C) Timing
Table 11-36. I
2
C Timing Requirements
(1)
(see Figure 11-32)
STANDARD MODE FAST MODE
NO. MIN MAX MIN MAX UNIT
1 t
c(SCL)
Cycle time, SCL 10 2.5 µs
2 Setup time, SCL high before SDA low (for a repeated START
t
su(SCLH-SDAL)
4.7 0.6 µs
condition)
3 Hold time, SCL low after SDA low (for a START and a
t
h(SDAL-SCLL)
4 0.6 µs
repeated START condition)
4 t
w(SCLL)
Pulse duration, SCL low 4.7 1.3 µs
5 t
w(SCLH)
Pulse duration, SCL high 4 0.6 µs
6 t
su(SDAV-SCLH)
Setup time, SDA valid before SCL high 250 100
(2)
ns
7 t
h(SCLL-SDAV)
Hold time, SDA valid after SCL low (for I
2
C bus devices) 0
(3)
3.45 0
(3)
0.9
(4)
µs
8 Pulse duration, SDA high between STOP and START
t
w(SDAH)
4.7 1.3 µs
conditions
9 t
r(SDA)
Rise time, SDA 1000 20 + 0.1C
b
(5)
300 ns
10 t
r(SCL)
Rise time, SCL 1000 20 + 0.1C
b
(5)
300 ns
11 t
f(SDA)
Fall time, SDA 300 20 + 0.1C
b
(5)
300 ns
12 t
f(SCL)
Fall time, SCL 300 20 + 0.1C
b
(5)
300 ns
(1) The I
2
C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A Fast-mode I
2
C-bus device can be used in a Standard-mode I
2
C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then
be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line t
r
max + t
su(SDA-SCLH)
= 1000 + 250 = 1250 ns
(according to the Standard-mode I
2
C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IHmin
of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum t
h(SDA-SCLL)
has to be met only if the device does not stretch the low period [t
w(SCLL)
] of the SCL signal.
(5) C
b
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
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