Clock
Prescale
I CPSC
2
Peripheral Clock
(CPU/6)
I CCLKH
2
Generator
Bit Clock
I CCLKL
2
Noise
Filter
SCL
I CXSR
2
I CDXR
2
Transmit
Transmit
Shift
Transmit
Buffer
I CDRR
2
Shift
I CRSR
2
Receive
Buffer
Receive
Receive
Filter
SDA
I C Data
2
Noise
I COAR
2
I CSAR
2
Slave
Address
Control
Address
Own
I CMDR
2
I CCNT
2
Mode
Data
Count
Vector
Interrupt
Interrupt
Status
I CIVR
2
I CSTR
2
Mask/Status
Interrupt
I CIMR
2
Interrupt/DMA
I C Module
2
I C Clock
2
Shading denotes control/status registers.
I CEMDR
2
Extended
Mode
66AK2E05, 66AK2E02
www.ti.com
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
11.10.1 I
2
C Device-Specific Information
The device includes multiple I
2
C peripheral modules.
NOTE
When using the I
2
C module, ensure there are external pullup resistors on the SDA and SCL
pins.
The I
2
C modules on the 66AK2E0x may be used by the SoC to control local peripheral ICs (DACs, ADCs,
etc.), communicate with other controllers in a system, or to implement a user interface.
The I
2
C port supports:
• Compatibility with Philips I
2
C specification revision 2.1 (January 2000)
• Fast mode up to 400 kbps (no fail-safe I/O buffers)
• Noise filter to remove noise of 50 ns or less
• 7-bit and 10-bit device addressing modes
• Multi-master (transmit/receive) and slave (transmit/receive) functionality
• Events: DMA, interrupt, or polling
• Slew-rate limited open-drain output buffers
Figure 11-31 shows a block diagram of the I
2
C module.
Figure 11-31. I
2
C Module Block Diagram
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