66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
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• 64-bit:Eight 8-bit SDRAMs
• 32-bit:Two 16-bit SDRAMs
• 32-bit: Four 8-bit SDRAMs
• 16-bit:One 16-bit SDRAM
• 16-bit:Two 8-bit SDRAMs
The approach to specifying interface timing for the DDR3 memory bus is different than on other interfaces
such as I
2
C or SPI. For these other interfaces, the device timing was specified in terms of data manual
specifications and I/O buffer information specification (IBIS) models. For the DDR3 memory bus, the
approach is to specify compatible DDR3 devices and provide the printed circuit board (PCB) solution and
guidelines directly to the user.
A race condition may exist when certain masters write data to the DDR3 memory controller. For example,
if master A passes a software message via a buffer in external memory and does not wait for an indication
that the write completes before signaling to master B that the message is ready, when master B attempts
to read the software message, the master B read may bypass the master A write. Thus, master B may
read stale data and receive an incorrect message.
Some master peripherals (e.g., EDMA3 transfer controllers with TCCMOD=0) always wait for the write to
complete before signaling an interrupt to the system, thus avoiding this race condition. For masters that do
not have a hardware specification of write-read ordering, it may be necessary to specify data ordering in
the software.
If master A does not wait for an indication that a write is complete, it must perform the following
workaround:
1. Perform the required write to DDR3 memory space.
2. Perform a dummy write to the DDR3 memory controller module ID and revision register.
3. Perform a dummy read to the DDR3 memory controller module ID and revision register.
4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The
completion of the read in step 3 ensures that the previous write was done.
11.9.2 DDR3 Slew Rate Control
The DDR3 slew rate is controlled by use of the PHY registers. See theKeyStone Architecture DDR3
Memory Controller User's Guide SPRUGV8 for details.
11.9.3 DDR3 Memory Controller Electrical Data/Timing
The DDR3 Design Requirements for KeyStone Devices application report SPRABI1 specifies a complete
DDR3 interface solution as well as a list of compatible DDR3 devices. The DDR3 electrical requirements
are fully specified in the DDR3 JEDEC Specification JESD79-3C. TI has performed the simulation and
system characterization to ensure all DDR3 interface timings in this solution are met. Therefore, no
electrical data/timing information is supplied here for this interface.
NOTE
TI supports only designs that follow the board design guidelines outlined in the application
report.
11.10 I
2
C Peripheral
The Inter-Integrated Circuit (I
2
C) module provides an interface between SoC and other devices compliant
with Philips Semiconductors (now NXP Semiconductors) Inter-Integrated Circuit bus specification version
2.1. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from
the device through the I
2
C module.
246 66AK2E0x Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated
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