3
LRESETNMIEN
/LRESET
NMI
1 2
66AK2E05, 66AK2E02
www.ti.com
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Figure 11-29. NETCP PLL Timing
11.8 External Interrupts
11.8.1 External Interrupts Electrical Data/Timing
Table 11-34. NMI and LRESET Timing Requirements
(1)
(see Figure 11-30)
No. Min Max Unit
1 tsu(LRESET-LRESETNMIEN) Setup time - LRESET valid before LRESETNMIEN low 12*P ns
1 tsu(NMI-LRESETNMIEN) Setup time - NMI valid before LRESETNMIEN low 12*P ns
2 th(LRESETNMIEN-LRESET) Hold time - LRESET valid after LRESETNMIEN high 12*P ns
2 th(LRESETNMIEN-NMI) Hold time - NMI valid after LRESETNMIEN high 12*P ns
3 tw(LRESETNMIEN) Pulsewidth - LRESETNMIEN low width 12*P ns
(1) P = 1/SYSCLK1 clock frequency in ns.
Figure 11-30. NMI and LRESET Timing
11.9 DDR3 Memory Controller
The 72-bit DDR3 Memory Controller bus of the 66AK2E0x is used to interface to JEDEC standard-
compliant DDR3 SDRAM devices. The DDR3 external bus interfaces only to DDR3 SDRAM devices and
does not share the bus with any other type of peripheral.
11.9.1 DDR3 Memory Controller Device-Specific Information
The 66AK2E0x includes one 64-bit wide, 1.5-V DDR3 SDRAM EMIF interface. The DDR3 interface can
operate at 800 mega transfers per second (MTS), 1033 MTS, 1333 MTS, and 1600 MTS.
Due to the complicated nature of the interface, a limited number of topologies are supported to provide a
16-bit, 32-bit, or 64-bit interface.
The DDR3 electrical requirements are fully specified in the DDR JEDEC Specification JESD79-3C.
Standard DDR3 SDRAMs are available in 8-bit and 16-bit versions allowing for the following bank
topologies to be supported by the interface:
• 72-bit: Five 16-bit SDRAMs (including 8 bits of ECC)
• 72-bit: Nine 8-bit SDRAMs (including 8 bits of ECC)
• 36-bit: Three 16-bit SDRAMs (including 4 bits of ECC)
• 36-bit:Five 8-bit SDRAMs (including 4 bits of ECC)
• 64-bit:Four 16-bit SDRAMs
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