4
POR
RESET
RESETFULL
RESETSTAT
2
3
POR
RESET
RESETFULL
RESETSTAT
1
66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
www.ti.com
Table 11-10. Reset Timing Requirements
(1)
(see Figure 11-4 and Figure 11-5)
NO. MIN MAX UNIT
RESETFULL Pin Reset
1 tw(RESETFULL) Pulse width - pulse width RESETFULL low 500C ns
Soft/Hard-Reset
2 tw(RESET) Pulse width - pulse width RESET low 500C ns
(1) C = 1/SYSCLK1 clock frequency in ns
Table 11-11. Reset Switching Characteristics
(1)
(see Figure 11-4 and Figure 11-5)
NO. PARAMETER MIN MAX UNIT
RESETFULL Pin Reset
3 td(RESETFULLH- Delay time - RESETSTAT high after RESETFULL high 50000C ns
RESETSTATH)
Soft/Hard Reset
4 td(RESETH-RESETSTATH) Delay time - RESETSTAT high after RESET high 50000C ns
(1) C = 1/SYSCLK1 clock frequency in ns
Figure 11-4. RESETFULL Reset Timing
Figure 11-5. Soft/Hard Reset Timing
Table 11-12. Boot Configuration Timing Requirements
(1)
(see Figure 11-6)
NO. MIN MAX UNIT
1 tsu(GPIOn-RESETFULL) Setup time - GPIO valid before RESETFULL asserted 12C ns
2 th(RESETFULL-GPIOn) Hold time - GPIO valid after RESETFULL asserted 12C ns
(1) C = 1/SYSCLK1 clock frequency in ns.
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