66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
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NOTE
To most of the device, reset is de-asserted only when the POR and RESET pins are both
de-asserted (driven high). Therefore, in the sequence described above, if the RESET pin is
held low past the low period of the POR pin, most of the device will remain in reset. The
RESET pin should not be tied to the POR pin.
11.4.2 Hard Reset
A hard reset will reset everything on the device except the PLLs, test logic, emulation logic, and reset-
isolated modules. POR should also remain de-asserted during this time.
Hard reset is initiated by the following:
• RESET pin
• RSCTRL Register in the PLL Controller
• Watchdog timer
• Emulation
By default, all the initiators listed above are configured to generate a hard reset. Except for emulation, all
of the other three initiators can be configured in the RSCFG Register in the PLL Controller to generate soft
resets.
The following sequence must be followed during a hard reset:
1. The RESET pin is asserted (driven low) for a minimum of 24 CLKIN1 cycles. During this time, the
RESET signal propagates to all modules (except those specifically mentioned above). To prevent off-
chip contention during the warm reset, all I/O must be Hi-Z for modules affected by RESET.
2. Once all logic is reset, RESETSTAT is asserted (driven low) to denote that the device is in reset.
3. The RESET pin can now be released. A minimal device initialization begins to occur. Note that
configuration pins are not re-latched and clocking is unaffected within the device.
4. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high).
NOTE
The POR pin should be held inactive (high) throughout the warm reset sequence. Otherwise,
if POR is activated (brought low), the minimum POR pulse width must be met. The RESET
pin should not be tied to the POR pin.
11.4.3 Soft Reset
A soft reset behaves like a hard reset except that the EMIF16 MMRs, DDR3 EMIF MMRs, PCIe MMRs
sticky bits, and external memory content are retained. POR should also remain de-asserted during this
time.
Soft reset is initiated by the following:
• RESET pin
• RSCTRL Register in the PLL Controller
• Watchdog timer
In the case of a soft reset, the clock logic and the power control logic of the peripherals are not affected
and, therefore, the enabled/disabled state of the peripherals is not affected. On a soft reset, the DDR3
memory controller registers are not reset. If the user places the DDR3 SDRAM in self-refresh mode
before invoking the soft reset, the DDR3 SDRAM memory content is retained.
During a soft reset, the following occurs:
1. The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset propagates
through the system. Internal system clocks are not affected. PLLs remain locked.
224 66AK2E0x Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated
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