66AK2E05, 66AK2E02
www.ti.com
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 11-9. Reset Types (continued)
TYPE INITIATOR EFFECT(S)
Soft reset behaves like hard reset except that PCIe MMRs (memory-mapped registers) and
RESET pin
DDR3 EMIF MMRs contents are retained.
PLLCTL Register
Soft reset
By default, these initiators are configured as hard reset, but can be configured as soft reset
(RSCTRL)
in the RSCFG Register of the PLL Controller. Contents of the DDR3 SDRAM memory can
Watchdog timers
be retained during a soft reset if the SDRAM is placed in self-refresh mode.
Local reset LRESET pin Resets the C66x CorePac, without disturbing clock alignment or memory contents. The
Watchdog timer timeout device configuration pins are not relatched.
LPSC MMRs
11.4.1 Power-on Reset
Power-on reset is used to reset the entire device, including the test and emulation logic.
Power-on reset is initiated by the following:
1. POR pin
2. RESETFULL pin
During power-up, the POR pin must be asserted (driven low) until the power supplies have reached their
normal operating conditions. Also a RESETFULL pin is provided to allow reset of the entire device,
including the reset-isolated logic, when the device is already powered up. For this reason, the
RESETFULL pin, unlike POR, should be driven by the on-board host control other than the power good
circuitry. For power-on reset, the Core PLL Controller comes up in bypass mode and the PLL is not
enabled. Other resets do not affect the state of the PLL or the dividers in the PLL Controller.
The following sequence must be followed during a power-on reset:
1. Wait for all power supplies to reach normal operating conditions while keeping the POR and
RESETFULL pins asserted (driven low). While POR is asserted, all pins except RESETSTAT will be
set to high-impedance. After the POR pin is deasserted (driven high), all Z group pins, low group pins,
and high group pins are set to their reset state and remain in their reset state until otherwise
configured by their respective peripheral. All peripherals that are power-managed are disabled after a
power-on reset and must be enabled through the Device State Control Registers (for more details, see
Section 9.2.3).
2. Clocks are reset, and they are propagated throughout the chip to reset any logic that was using reset
synchronously. All logic is now reset and RESETSTAT is driven low, indicating that the device is in
reset.
3. POR and RESETFULL must be held active until all supplies on the board are stable, and then for at
least an additional period of time (as specified in Section 11.2.1) for the chip-level PLLs to lock.
4. The POR pin can now be de-asserted.
5. After the appropriate delay, the RESETFULL pin can now be de-asserted. Reset-sampled pin values
are latched at this point. Then, all chip-level PLLs are taken out of reset, locking sequences begin, and
all power-on device initialization processes begin.
6. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high). By this time,
the DDR3 PLL has completed its locking sequences and are supplying a valid clock. The system
clocks of the PLL controllers are allowed to finish their current cycles and then are paused for 10
cycles of their respective system reference clocks. After the pause, the system clocks are restarted at
their default divide-by settings.
7. The device is now out of reset and code execution begins as dictated by the selected boot mode.
Copyright © 2012–2015, Texas Instruments Incorporated 66AK2E0x Peripheral Information and Electrical Specifications 223
Submit Documentation Feedback
Product Folder Links: 66AK2E05 66AK2E02
