66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
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Table 11-8. PSC Register Memory Map (continued)
OFFSET REGISTER DESCRIPTION
0xA8C MDCTL35 Module Control Register 35
0xA90 MDCTL36 Module Control Register 36
0xA94 MDCTL37 Module Control Register 37
0xA98 MDCTL38 Module Control Register 38
0xA9C MDCTL39 Module Control Register 39
0xAA0 MDCTL40 Module Control Register 40
0xAA4 MDCTL41 Module Control Register 41
0xAA8 MDCTL42 Module Control Register 42
0xAAC MDCTL43 Module Control Register 43
0xAB0 MDCTL44 Module Control Register 44
0xAB4 MDCTL45 Module Control Register 45
0xAB8 MDCTL46 Module Control Register 46
0xABC MDCTL47 Module Control Register 47
0xAC0 MDCTL48 Module Control Register 48
0xAC4 MDCTL49 Module Control Register 49
0xAC8 MDCTL50 Module Control Register 50
0xACC MDCTL51 Module Control Register 51
0xAD0 MDCTL52 Module Control Register 52
0xAD4 - 0xFFC Reserved Reserved
11.4 Reset Controller
The reset controller detects the different type of resets supported on the 66AK2E0x device and manages
the distribution of those resets throughout the device. The device has the following types of resets:
• Power-on reset
• Hard reset
• Soft reset
• Local reset
Table 11-9 explains further the types of reset, the reset initiator, and the effects of each reset on the
device. For more information on the effects of each reset on the PLL controllers and their clocks, see
Section 11.4.8.
Table 11-9. Reset Types
TYPE INITIATOR EFFECT(S)
POR pin Resets the entire chip including the test and emulation logic. The device configuration pins
Power-on reset
RESETFULL pin are latched only during power-on reset.
Hard reset resets everything except for test, emulation logic, and reset isolation modules.
This reset is different from power-on reset in that the PLL Controller assumes power and
clocks are stable when a hard reset is asserted. The device configurations pins are not
RESET pin
relatched.
PLLCTL Register
Hard reset (RSCTRL)
(1)
Emulation-initiated reset is always a hard reset.
Watchdog timers
By default, these initiators are configured as hard reset, but can be configured (except
Emulation
emulation) as a soft reset in the RSCFG Register of the PLL Controller. Contents of the
DDR3 SDRAM memory can be retained during a hard reset if the SDRAM is placed in self-
refresh mode.
(1) All masters in the device have access to the PLL Control Registers.
222 66AK2E0x Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated
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