32KB L1
P-Cache
32KB L1
D-Cache
ARM
A15
L2 Cache Control and Snoop Control Unit
4 MB L2 Cache
Timer 0 - 3
Generic
Interrupt
Controller
400
Global
Time Base
Counter
VBUSP2AXI
Bridge
ARM INTC
KeyStone II ARM CorePac (Single Core)
TeraNet
(CFG)
480 SPI
Interrupts
IRQ,
FIQ,
VIRQ,
VFIQ
4
PPI
64
Bits
Debug
CTM
CTI (´4)
AXI-VBUS
Master
ARM
Trace
ATB
PTM (´4)
APB MUX
Debug
SubSystem
APB
APB
ATB
OCP
VBUSP
TeraNet
(DMA)
256b
VBUSM
MSMC
DDR3
ARM
VBUSP
Registers
VBUSP
TeraNet
(CFG)
Boot Config
Main PLL
PSC
Endian
CFG
ARM
CorePac
Clock
ARM
A15 Core
Clock
ARM
ATB
CTI/CTM
STM
APB
ARM Cluster
66AK2E02
66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
www.ti.com
Figure 5-2. 66AK2E02 ARM CorePac Block Diagram
22 ARM CorePac Copyright © 2012–2015, Texas Instruments Incorporated
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