66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
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Table 11-7. Clock Domains (continued)
LPSC NUMBER MODULE(S) NOTES
35 Reserved Reserved
36 Reserved Reserved
37 Reserved Reserved
38 Reserved Reserved
39 Reserved Reserved
40 Reserved Reserved
41 Reserved Reserved
42 Reserved Reserved
43 Reserved Reserved
44 Reserved Reserved
45 Reserved Reserved
46 Reserved Reserved
47 Reserved Reserved
48 Reserved Reserved
49 Reserved Reserved
50 10GbE Software control
51 ARM Smart Reflex Software control
52 ARM CorePac Software control
No LPSC Bootcfg, PSC, and PLL Controller These modules do not use LPSC
11.3.3 PSC Register Memory Map
Table 11-8 shows the PSC Register memory map.
Table 11-8. PSC Register Memory Map
OFFSET REGISTER DESCRIPTION
0x000 PID Peripheral Identification Register
0x004 - 0x010 Reserved Reserved
0x014 VCNTLID Voltage Control Identification Register
0x018 - 0x11C Reserved Reserved
0x120 PTCMD Power Domain Transition Command Register
0x124 Reserved Reserved
0x128 PTSTAT Power Domain Transition Status Register
0x12C - 0x1FC Reserved Reserved
0x200 PDSTAT0 Power Domain Status Register 0
0x204 PDSTAT1 Power Domain Status Register 1
0x208 PDSTAT2 Power Domain Status Register 2
0x20C PDSTAT3 Power Domain Status Register 3
0x210 PDSTAT4 Power Domain Status Register 4
0x214 PDSTAT5 Power Domain Status Register 5
0x218 PDSTAT6 Power Domain Status Register 6
0x21C PDSTAT7 Power Domain Status Register 7
0x220 PDSTAT8 Power Domain Status Register 8
0x224 PDSTAT9 Power Domain Status Register 9
0x228 PDSTAT10 Power Domain Status Register 10
0x22C PDSTAT11 Power Domain Status Register 11
0x230 PDSTAT12 Power Domain Status Register 12
0x234 PDSTAT13 Power Domain Status Register 13
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