66AK2E05, 66AK2E02
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 11-6. 66AK2Ex Power Domains (continued)
DOMAIN BLOCK(S) NOTE POWER CONNECTION
30 ARM Smart Reflex Logic can be powered down Software control
31 ARM CorePac Logic can be powered down Software control
11.3.2 Clock Domains
Clock gating to each logic block is managed by the Local Power Sleep Controllers (LPSCs) of each
module. For modules with a dedicated clock or multiple clocks, the LPSC communicates with the PLL
controller to enable and disable that module's clock(s) at the source. For modules that share a clock with
other modules, the LPSC controls the clock gating logic for each module.
Table 11-7 shows the 66AK2E0x clock domains.
Table 11-7. Clock Domains
LPSC NUMBER MODULE(S) NOTES
0 Shared LPSC for all peripherals other than those listed in this table Always on
1 USB_1
2 USB_0 Software control
3 EMIF16 and SPI Software control
4 TSIP Software control
5 Debug subsystem and tracers Software control
6 Reserved Always on
7 Packet Accelerator Software control
8 Ethernet SGMIIs Software control
9 Security Accelerator Software control
10 PCIe_0 Software control
11 Reserved
12 HyperLink Software control
13 SmartReflex Always on
14 MSMC RAM Software control
15 C66x CorePac0 Always on
16 Reserved
17 Reserved
18 Reserved
19 Reserved
20 Reserved
21 Reserved
22 Reserved
23 DDR3 EMIF Software control
24 Reserved
25 Reserved Reserved
26 Reserved Reserved
27 PCIe_1 Reserved
28 Reserved Reserved
29 Reserved Reserved
30 Reserved Reserved
31 Reserved Reserved
32 Reserved Reserved
33 Reserved Reserved
34 Reserved Reserved
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