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66AK2E05XABD4

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型号: 66AK2E05XABD4
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功能描述: 66AK2E0x Multicore DSPARM KeyStone II System-on-Chip (SoC)
PDF文件大小: 1546.9 Kbytes
PDF页数: 共282页
制造商: TI[Texas Instruments]
制造商LOGO: TI[Texas Instruments] LOGO
制造商网址: http://www.ti.com
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120%
VCNTL[4:2]
VCNTL[5]
1
2
4
LSB VID[2:0] MSB VID[5:3]
3
66AK2E05, 66AK2E02
www.ti.com
SPRS865D NOVEMBER 2012REVISED MARCH 2015
11.2.4 SmartReflex
Increasing the device complexity increases its power consumption. With higher clock rates and increased
performance comes an inevitable penalty: increasing leakage currents. Leakage currents are present in
any powered circuit, independent of clock rates and usage scenarios. This static power consumption is
mainly determined by transistor type and process technology. Higher clock rates also increase dynamic
power, which is the power used when transistors switch. The dynamic power depends mainly on a specific
usage scenario, clock rates, and I/O activity.
Texas Instruments SmartReflex technology is used to decrease both static and dynamic power
consumption while maintaining the device performance. SmartReflex in the
66AK2E0x device is a feature that allows the core voltage to be optimized based on the process corner of
the device. This requires a voltage regulator for each 66AK2E0x device.
To help maximize performance and minimize power consumption of the device, SmartReflex is required to
be implemented. The voltage selection can be accomplished using 4 VCNTL pins or 6 VCNTL pins
(depending on power supply device being used), which are used to select the output voltage of the core
voltage regulator.
For information on implementation of SmartReflex see the Power Consumption Summary for KeyStone
TCI66x Devices application report (SPRABL4) and the Hardware Design Guide for KeyStone II Devices
application report (SPRABV0).
Table 11-5. SmartReflex 4-Pin 6-bit VID Interface Switching Characteristics
(see Figure 11-3)
NO. PARAMETER MIN MAX UNIT
1 td(VCNTL[4:2]-VCNTL[5]) Delay time - VCNTL[4:2] valid after VCNTL[5] low 300.00 ns
2 toh(VCNTL[5]-VCNTL[4:2]) Output hold time - VCNTL[4:2] valid after VCNTL[5] 0.07 172020C
(1)
ms
3 td(VCNTL[4:2]-VCNTL[5]) Delay time - VCNTL[4:2] valid after VCNTL[5] high 300.00 ns
4 toh(VCNTL[5]-VCNTL[2:0) Output hold time - VCNTL[4:2] valid after VCNTL[5] high 0.07 172020C ms
(1) C = 1/SYSCLK1 frequency, in ms (see Figure 11-9)
Figure 11-3. SmartReflex 4-Pin 6-Bit VID Interface Timing
11.2.5 Monitor Points
Two pairs of monitor points for the CVDD voltage level are provided. Both CVDDCMON and CVDDTMON
are connected directly to the CVDD supply plane on the die itself. VSSCMON and VSSTMON are
connected to the ground plane on the die. These pairs provide the best measurement points for the
voltage at the silicon. They also provide the best point to connect the remote sense lines for the CVDD
power supply. The use of a power supply with a differential remote sense input is highly desirable. The
positive remote sense line should be connected to CVDDCMON and the negative remote sense line
should be connected to VSSCMON. CVDDTMON and VSSTMON can be used as an alternative but
always use either the CMON pair or the TMON pair. If the power supply remote sense is not differential
CVDDCMON or CVDDTMON can be connected to the sense line.
Copyright © 2012–2015, Texas Instruments Incorporated 66AK2E0x Peripheral Information and Electrical Specifications 215
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Product Folder Links: 66AK2E05 66AK2E02
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