RESET
RESETFULL
1
POR
CVDD
CVDD1
DVDD15
SYSCLK1
DDRCLKOUT
RESETSTAT
Power Stabilization Phase Device Initialization Phase
8
2a
Configuration
Inputs
10
9
11 12
3a
3b
7
USBxDVDD33
5
6
1
2
3
4
5
6
VDDAHV
AVDDAx
DVDD18
VDDALV
USBxVP
USBxVPTX
2
4
3
66AK2E05, 66AK2E02
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Figure 11-2. IO-Before-Core Power Sequencing
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