66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
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11.2.1.2 IO-Before-Core Power Sequencing
The timing diagram for IO-before-core power sequencing is shown in Figure 11-2 and defined in Table 11-
3.
NOTE
TI recommends a maximum of 100 ms between one power rail being valid, and the next
power rail in the sequence starting to ramp.
Table 11-3. IO-Before-Core Power Sequencing
ITEM SYSTEM STATE
1 Begin Power Stabilization Phase
• VDDAHV, AVDDAx and DVDD18 ramp up.
• POR must be held low through the power stabilization phase. Because POR is low, all the core logic that has asynchronous
reset (created from POR ) is put into the reset state.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
2
• CVDD (core AVS) ramps within 80 ms from the time ADDAHV, AVDDAx and DVDD18 are valid.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
2a
• RESET may be driven high any time after DVDD18 is at a valid level. must be high before POR is driven high.
3
• CVDD1 (core constant) ramp at the same time or within 80 ms following CVDD. Although ramping CVDD1 simultaneously
with CVDD is permitted, the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.
• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 should trail CVDD as
this will ensure that the Word Lines (WLs) in the memories are turned off and there is no current through the memory bit
cells. If, however, CVDD1 (core constant) ramp up before CVDD (core AVS), then the worst-case current could be on the
order of twice the specified draw of CVDD1.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
3a
• Once CVDD is valid, the clock drivers can be enabled. Although the clock inputs are not necessary at this time, they should
either be driven with a valid clock or held in a static state.
3b
• The DDRCLK and SYSCLK1 may begin to toggle anytime between when CVDD is at a valid level and the setup time before
POR goes high specified by item 8.
4
• DVDD15 can ramp up within 80 ms of when CVDD1 is valid.
• RESETSTAT is driven low once the DVDD18 supply is available.
• All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or
bidirectional pin before DVDD18 is valid could cause damage to the device.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
5
• VDDALV, VDDUSBx, USBxVP and USBxVPTX should ramp up within 80 ms of when DVDD15 is valid.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
6
• USBxDVDD33 supply is ramped up within 80 ms of when VDDALV, VDDUSBx, USBxVP and USBxVPTX are valid.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
7
• POR must continue to remain low for at least 100 μs after all power rails have stabilized.
End power stabilization phase
8
• Device initialization requires 500 SYSCLK1 periods after the Power Stabilization Phase. The maximum clock period is 33.33
nsec, so a delay of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire
16 μs.
9
• RESETFULL must be held low for at least 24 transitions of the SYSCLK1 after POR has stabilized at a high level.
10
• The rising edge of the RESETFULL will remove the reset to the efuse farm allowing the scan to begin.
• Once device initialization and the efuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be
10000 to 50000 clock cycles.
End device initialization phase
11
• GPIO configuration bits must be valid for at least 12 transitions of the SYSCLK1 before the rising edge of RESETFULL.
12
• GPIO configuration bits must be held valid for at least 12 transitions of the SYSCLK1 after the rising edge of RESETFULL.
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