RESET
RESETFULL
POR
CVDD
CVDD1
DVDD15
USBxDVDD33
SYSCLK1
DDRCLKOUT
RESETSTAT
Power Stabilization Phase Device Initialization Phase
3a
2a
2d
Configuration
Inputs
9
8
11
1
VDDALV
USBxVP
USBxVPTX
2b
VDDAHV
AVDDAx
DVDD18
3
7
2c
10
1
2
3
4
5
6
4
5
66AK2E05, 66AK2E02
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Figure 11-1. Core-Before-IO Power Sequencing
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