66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
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Table 11-2. Core-Before-IO Power Sequencing (continued)
ITEM SYSTEM STATE
2b
• VDDAHV, AVDDAx and DVDD18 ramp at the same time or shortly following CVDD. DVDD18 must be enabled within 80 ms
of CVDD valid and must ramp monotonically and reach a stable level in 20ms or less. This results in no more than 100
ms from the time when CVDD is valid to the time when DVDD18 is valid.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
• The timing for DVDD18/ADDAVH/AVDDAx is based on CVDD valid. DVDD18/ADDAVH/AVDDAx and CVDD1 may be
enabled at the same time but do not need to ramp simultaneously. DVDD18/ADDAVH/AVDDAx may be valid before or after
CVDD1 is valid, as long as the timing above is met.
2c
• Once CVDD is valid, the clock drivers can be enabled. Although the clock inputs are not necessary at this time, they should
either be driven with a valid clock or be held in a static state with one leg high and one leg low.
2d
• The DDRCLK and SYSCLK1 may begin to toggle anytime between when CVDD is at a valid level and the setup time before
POR goes high specified by item 7.
3
• DVDD15 can ramp up within 80ms of when DVDD18 is valid.
• RESETSTAT is driven low once the DVDD18 supply is available.
• All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or
bidirectional pin before DVDD18 is valid could cause damage to the device.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
3a
• RESET may be driven high any time after DVDD18 is at a valid level. RESET must be high before POR is driven high.
4
• VDDALV, VDDUSBx, USBxVP and USBxVPTX ramp up within 80ms of when DVDD15 is valid.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
5
• USBxDVDD33 supply is ramped up within 80 ms of when VDDALV, VDDUSBx, USBxVP and USBxVPTX are valid.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
6
• POR must continue to remain low for at least 100 μs after all power rails have stabilized.
End power stabilization phase
7
• Device initialization requires 500 SYSCLK1 periods after the Power Stabilization Phase. The maximum clock period is 33.33
nsec, so a delay of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire
16 μs.
8
• RESETFULL must be held low for at least 24 transitions of the SYSCLK1 after POR has stabilized at a high level.
9
• The rising edge of the RESETFULL will remove the reset to the eFuse farm allowing the scan to begin.
• Once device initialization and the eFuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be
10000 to 50000 clock cycles.
End device initialization phase
10
• GPIO configuration bits must be valid for at least 12 transitions of the SYSCLK1 before the rising edge of RESETFULL.
11
• GPIO configuration bits must be held valid for at least 12 transitions of the SYSCLK1 after the rising edge of RESETFULL.
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