66AK2E05, 66AK2E02
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Figure 9-40. USB_PHY_CTL3 Register
31 30 29 23
Reserved PHY_PC_PCS_TX_SWING_FULL
R-0 R/W-1111000
22 17 16 11 10 5 4 0
PHY_PC_PCS_TX_DEEMPH_6DB Reserved PHY_PC_PCS_TX_DEEMPH_3P5DB PHY_PC_LOS_LEVEL
R/W-100000 R-0 R/W-010101 R/W-01001
Legend: R = Read only; R/W = Read/Write, -n = value after reset
Table 9-60. USB_PHY_CTL3 Register Field Descriptions
Bit Field Description
31-30 Reserved Reserved
29-23 PHY_PC_PCS_TX_SWING_ Tx Amplitude (Full Swing Mode).
FULL
Sets the launch amplitude of the transmitter. It can be used to tune Rx eye for compliance.
22-17 PHY_PC_PCS_TX_DEEMPH_ Tx De-Emphasis at 6 dB.
6DB
Sets the Tx driver de-emphasis value when pipeP_tx_deemph[1:0] is set to 10b (according to
the PIPE3 specification). This bus is provided for completeness and as a second potential
launch amplitude.
16-11 Reserved Reserved
10-5 PHY_PC_PCS_TX_DEEMPH_ Tx De-Emphasis at 3.5 dB.
3P5DB
Sets the Tx driver de-emphasis value when pipeP_tx_deemph[1:0] is set to 10b (according to
the PIPE3 specification). Can be used for Rx eye compliance.
4-0 PHY_PC_LOS_LEVEL Loss-of-Signal Detector Sensitivity Level Control.
Sets the LOS detection threshold level. This signal must be set to 0x9.
Figure 9-41. USB_PHY_CTL4 Register
31 30 29 28
PHY_SSC_EN PHY_REF_USE_PAD PHY_REF_SSP_EN PHY_MPLL_REFSSC_CLK_EN
R/W-1 R/W-0 R/W-0 R/W-0
27 22 21 20 19 18 17
PHY_FSEL PHY_RETENABLEN PHY_REFCLKSEL PHY_COMMONONN Reserved
R/W-100111 R/W-1 R/W-10 R/W-0 R-0
16 15 14 12 11 7 6 0
PHY_OTG_VBUSVLDEXTSEL PHY_OTG_ PHY_PC_TX_VBOOST PHY_PC_LANE0_TX_TERM_ Reserved
OTGDISABLE _LVL OFFSET
R/W-0 R/W-1 R/W-100 R/W-00000 R-0
Legend: R = Read only; R/W = Read/Write, -n = value after reset
Table 9-61. USB_PHY_CTL4 Register Field Descriptions
Bit Field Description
31 PHY_SSC_EN Spread Spectrum Enable.
Enables spread spectrum clock production (0.5% down-spread at ~31.5 KHz) in the USB3.0
PHY. If the reference clock already has spread spectrum applied, ssc_en must be de-asserted.
30 PHY_REF_USE_PAD Select Reference Clock Connected to ref_pad_clk_{p,m}.
When asserted, selects the external ref_pad_clk_{p,m} inputs as the reference clock source.
When de-asserted, ref_alt_clk_{p,m} are selected for an on-chip reference clock source.
29 PHY_REF_SSP_EN Reference Clock Enables for SS function.
Enables the reference clock to the prescaler. The ref_ssp_en signal must remain de asserted
until the reference clock is running at the appropriate frequency, at which point ref_ssp_en can
be asserted. For lower power states, ref_ssp_en can also be de asserted.
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