66AK2E05, 66AK2E02
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 9-56. SYNECLK_PINCTL Register Descriptions
Bit Field Description
31-7 Reserved Reserved
6-4 TSRXCLKOUT1SEL
• 000 - SGMII Lane 0 rxbclk
• 001 - SGMII Lane 1 rxbclk
• 010 - SGMII Lane 2 rxbclk
• 011 - SGMII Lane 3 rxbclk
• 100 - XFI Lane 0 rxbclk
• 101 - XFI Lane 1 rxbclk
• 110 - XFI Lane 2 rxbclk
• 111 - XFI Lane 3 rxbclk
3 Reserved Reserved
2-0 TSRXCLKOUT0SEL
• 000 - SGMII Lane 0 rxbclk
• 001 - SGMII Lane 1 rxbclk
• 010 - SGMII Lane 2 rxbclk
• 011 - SGMII Lane 3 rxbclk
• 100 - XFI Lane 0 rxbclk
• 101 - XFI Lane 1 rxbclk
• 110 - XFI Lane 2 rxbclk
• 111 - XFI Lane 3 rxbclk
9.2.3.27 USB PHY Control (USB_PHY_CTLx) Registers
The following registers control the USB PHY.
Figure 9-37. USB_PHY_CTL0 Register
31 12 11
Reserved PHY_RTUNE_ACK
R-0 R-0
10 9 8 7 6 5
PHY_RTUNE_REQ Reserved PHY_TC_VATESTENB PHY_TC_TEST_POWERDOWN PHY_TC_TEST_POWERDOWN
_SSP _HSP
R/W-0 R-0 R/W-00 R/W-0 R/W-0
4 3 2 1 0
PHY_TC_LOOPBACKENB Reserved UTMI_VBAUSVLDEXT UTMI_TXBITSTUFFENH UTMI_TXBITSTUFFEN
R/W-0 R-0 R/W-0 R/W-0 R/W-0
Legend: R = Read only; W = Write only; -n = value after reset
Table 9-57. USB_PHY_CTL0 Register Field Descriptions
Bit Field Description
31-12 Reserved Reserved
11 PHY_RTUNE_ACK The PHY uses an external resistor to calibrate the termination impedances of the PHY's high-
speed inputs and outputs.
The resistor is shared between the USB2.0 high-speed outputs and the Super-speed I/O. Each
time the PHY is taken out of a reset, a termination calibration is performed. For SS link, the
calibration can also be requested externally by asserting the PHY_RTUNE_REQ. When the
calibration is complete, the PHY_RTUNE_ACK transitions low.
A resistor calibration on the SS link cannot be performed while the link is operational
10 PHY_RTUNE_REQ See PHY_RTUNE_ACK.
9 Reserved Reserved
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