66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
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9.2.3.24 Chip Miscellaneous Control (CHIP_MISC_CTL1) Register
Figure 9-34. Chip Miscellaneous Control Register (CHIP_MISC_CTL1)
31 15 14 13 0
Reserved IO_TRACE_SEL Reserved
R- 0000 0000 00000000 RW-0 RW-0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 9-54. Chip Miscellaneous Control Register (CHIP_MISC_CTL1) Field Descriptions
Bit Field Description
31-15 Reserved Reserved.
14 IO_TRACE_SEL This bit controls the pin muxing of GPIO[31:17] and EMU[33:19] pin
• 0 = GPIO[31:17] is selected
• 1 = EMU[33:19] pins is selected
13-0 Reserved
9.2.3.25 System Endian Status Register (SYSENDSTAT)
This register provides a way for reading the system endianness in an endian-neutral way. A zero value
indicates big endian and a non-zero value indicates little endian. The SYSENDSTAT register captures the
LENDIAN bootmode pin and is used by the BOOTROM to guide the bootflow. The value is latched on the
rising edge of POR or RESETFULL .
Figure 9-35. System Endian Status Register
31 1 0
Reserved SYSENDSTAT
R-0000 0000 0000 0000 0000 0000 0000 000 R-0
Legend: RW = Read/Write; -n = value after reset
Table 9-55. System Endian Status Register Descriptions
Bit Field Description
31-1 Reserved Reserved
0 SYSENDSTAT Reflects the same value as the LENDIAN bit in the DEVSTAT register.
• 0 - SoC is in Big Endian
• 1 - SoC is in Little Endian
9.2.3.26 SYNECLK_PINCTL Register
This register controls the routing of recovered clock signals from any Ethernet port (SGMII/XFI of the
multiport switches) to the clock output TSRXCLKOUT0/TSRXCLKOUT1.
Figure 9-36. SYNECLK_PINCTL Register
31 7 6 4 3 2 0
Reserved TSRXCLKOUT1SEL Reserved TSRXCLKOUT0SEL
R-0000 0000 0000 0000 0000 0000 0 RW-0 RW-0
Legend: RW = Read/Write; - n = value after reset
196 Device Boot and Configuration Copyright © 2012–2015, Texas Instruments Incorporated
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