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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 9-46. Device Speed Register Field Descriptions (continued)
Bit Field Description
11-0 ARMSPEED Indicates the speed of the ARM (read only)
• 0b0000 0000 0000 = 800 MHz
• 0b0000 0000 0001 = 1000 MHz
• 0b0000 0000 001x = 1200 MHz
• 0b0000 0000 01xx = 1350 MHz
• 0b0000 0000 1xxx = 1400 MHz
• 0b0000 0001 xxxx = 1500 MHz
• 0b0000 001x xxxx = 1400 MHz
• 0b0000 01xx xxxx = 1350.8 MHz
• 0b0000 1xxx xxxx = 1200 MHz
• 0b0001 xxxx xxxx= 1000 MHz
• 0b001x xxxx xxxx = 800 MHz
9.2.3.20 ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7
The registers defined in ARM Configuration Register 0 (ARMENDIAN_CFGr_0) and ARM Configuration
Register 1 (ARMENDIAN_CFGr_1) control the way Cortex-A15 processor core access to peripheral
MMRs shows up in the Cortex-A15 processor registers. The purpose is to provide an endian-invariant
view of the peripheral MMRs when performing a 32-bit access. (Only one of the eight register sets is
shown.)
Figure 9-30. ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7
31 8 7 0
BASEADDR Reserved
RW R-0000 0000
Legend: RW = Read/Write; R = Read only
Table 9-47. ARM Endian Configuration Register 0
Default Values
DEFAULT
ARM ENDIAN CONFIGURATION REGISTER 0 VALUES
ARMENDIAN_CFG0_0 0x0001C000
ARMENDIAN_CFG1_0 0x00020000
ARMENDIAN_CFG2_0 0x000BC000
ARMENDIAN_CFG3_0 0x00210000
ARMENDIAN_CFG4_0 0x00023A00
ARMENDIAN_CFG5_0 0x00240000
ARMENDIAN_CFG6_0 0x01000000
ARMENDIAN_CFG7_0 0xFFFFFF00
Table 9-48. ARM Endian Configuration Register 0 Field Descriptions
Bit Field Description
31-8 BASEADDR 24-bit Base Address of Configuration Region R
This base address defines the start of a contiguous block of Memory Mapped Register space for which a
word swap is done by the ARM CorePac bridge.
7-0 Reserved Reserved
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