66AK2E05, 66AK2E02
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
• Level 2 (L2) SRAM/Cache
• Memory-mapped registers configuration bus
The priority level for operations initiated within the C66x CorePac are declared through registers in the
CorePac. These operations are:
• DSP-initiated transfers
• User-programmed cache coherency operations
• IDMA-initiated transfers
The priority level for operations initiated outside the CorePac by system peripherals is declared through
the Priority Allocation Register (PRI_ALLOC). System peripherals with no fields in PRI_ALLOC have their
own registers to program their priorities.
More information on the bandwidth management features of the CorePac can be found in
theTMS320C66x DSP CorePac User's Guide (SPRUGW0).
4.4 Power-Down Control
The C66x CorePac supports the ability to power-down various parts of the CorePac. The power-down
controller (PDC) of the CorePac can be used to power down L1P, the cache control hardware, the DSP,
and the entire CorePac. These power-down features can be used to design systems for lower overall
system power requirements.
NOTE
The 66AK2E0x does not support power-down modes for the L2 memory at this time.
More information on the power-down features of the C66x CorePac can be found in the TMS320C66x
DSP CorePac User's Guide (SPRUGW0).
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