66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
www.ti.com
Table 9-40. IPC Generation Registers Field Descriptions (continued)
Bit Field Description
0 IPCG Reads return 0.
Writes:
• 0 = No effect
• 1 = Creates an interrupt pulse on device pin (host interrupt/event output in HOUT pin)
9.2.3.15 IPC Acknowledgment Host (IPCARH) Register
The IPCARH register facilitates external host interrupts. Operation and use of the IPCARH register is the
same as for other IPCAR registers. The IPC Acknowledgment Host Register is shown in Figure 9-25 and
described in Table 9-41.
Figure 9-25. Acknowledgment Register (IPCARH)
31 4 3 0
SRCC27 - SRCC0 Reserved
RW +0 (per bit field) R-0000
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 9-41. IPC Acknowledgment Register Field Descriptions
Bit Field Description
31-4 SRCCx Reads the return current value of the internal register bit.
Writes:
• 0 = No effect
• 1 = Clears both SRCCx and the corresponding SRCSx
3-0 Reserved Reserved
9.2.3.16 Timer Input Selection Register (TINPSEL)
The Timer Input Selection Register selects timer inputs and is shown in Figure 9-26 and described in
Table 9-42.
Figure 9-26. Timer Input Selection Register (TINPSEL)
31 30 29 28 27 26 25 24
TINPHSEL15 TINPLSEL15 TINPHSEL14 TINPLSEL14 TINPHSEL13 TINPLSEL13 TINPHSEL12 TINPLSEL12
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
23 22 21 20 19 18 17 16
TINPHSEL11 TINPLSEL11 TINPHSEL10 TINPLSEL10 TINPHSEL9 TINPLSEL9 TINPHSEL8 TINPLSEL8
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
15 2 1 0
Reserved TINPHSEL0 TINPLSEL0
R-0 RW-0 RW-0
LEGEND: R = Read only; RW = Read/Write; -n = value after reset
Table 9-42. Timer Input Selection Field Description
Bit Field Description
31 TINPHSEL15 Input select for TIMER15 high.
• 0 = TIMI0
• 1 = TIMI1
188 Device Boot and Configuration Copyright © 2012–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: 66AK2E05 66AK2E02
