66AK2E05, 66AK2E02
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
9.2.3.13 IPC Acknowledgment (IPCARx) Registers
The IPCARx registers facilitate inter-CorePac interrupt acknowledgment.
The 66AK2E05 device has five IPCARx registers and the 66AK2E02 has two IPCARx registers.These
registers also provide a Source ID facility by which up to 28 different sources of interrupts can be
identified. Allocation of source bits to source processor and meaning is entirely based on software
convention. The register field descriptions are given in the following tables. Virtually anything can be a
source for these registers as this is completely controlled by software. Any master that has access to
BOOTCFG module space can write to these registers. The IPC Acknowledgment Register is shown in the
following figure and table.
Figure 9-23. IPC Acknowledgment Registers (IPCARx)
31 4 3 0
SRCC27 - SRCC0 Reserved
RW +0 (per bit field) R-0000
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 9-39. IPC Acknowledgment Registers Field Descriptions
Bit Field Description
31-4 SRCCx Reads return current value of internal register bit.
Writes:
• 0 = No effect
• 1 = Clears both SRCCx and the corresponding SRCSx
3-0 Reserved Reserved
9.2.3.14 IPC Generation Host (IPCGRH) Register
The IPCGRH register facilitates interrupts to external hosts. Operation and use of the IPCGRH register is
the same as for other IPCGR registers. The interrupt output pulse created by the IPCGRH register
appears on device pin HOUT.
The host interrupt output pulse is stretched so that it is asserted for four bootcfg clock cycles (SYSCLK1/6)
followed by a deassertion of four bootcfg clock cycles. Generating the pulse results in a pulse-blocking
window that is eight SYSCLK1/6-cycles long. Back-to-back writes to the IPCRGH register with the IPCG
bit (bit 0) set, generates only one pulse if the back-to-back writes to IPCGRH are less than the eight
SYSCLK1/6 cycle window — the pulse blocking window. To generate back-to-back pulses, the back-to-
back writes to the IPCGRH register must be written after the eight SYSCLK1/6 cycle pulse-blocking
window has elapsed. The IPC Generation Host Register is shown in Figure 9-24 and described in Table 9-
40.
Figure 9-24. IPC Generation Registers (IPCGRH)
31 4 3 1 0
SRCS27 - SRCS0 Reserved IPCG
RW +0 (per bit field) R-000 RW +0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 9-40. IPC Generation Registers Field Descriptions
Bit Field Description
31-4 SRCSx Reads return current value of internal register bit.
Writes:
• 0 = No effect
• 1 = Sets both SRCSx and the corresponding SRCCx.
3-1 Reserved Reserved
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