66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
www.ti.com
Table 9-37. NMI Generation Register Field Descriptions
Bit Field Description
31-1 Reserved Reserved
0 NMIG Reads return 0
Writes:
• 0 = No effect
• 1 = Creates NMI pulse to the corresponding C66x CorePac — C66x CorePac0 for NMIGR0, etc.
9.2.3.12 IPC Generation (IPCGRx) Registers
The IPCGRx Registers facilitate inter-C66x CorePac interrupts.
The 66AK2E05 device has five IPCGRx registers (IPCGR0, IPCGR8-IPCGR11) and the 66AK2E02 has
two IPCGRx registers (IPCGR0 and IPCGR8). These registers can be used by external hosts or
CorePacs to generate interrupts to other CorePacs. A write of 1 to the IPCG field of the IPCGRx register
generates an interrupt pulse to the:
• C66x CorePac0
• ARM CorePac
These registers also provide a Source ID facility identifying up to 28 different sources of interrupts.
Allocation of source bits to source processor and meaning is entirely based on software convention. The
register field descriptions are given in the following tables. There can be numerous sources for these
registers as this is completely controlled by software. Any master that has access to BOOTCFG module
space can write to these registers. The IPC Generation Register is shown in Figure 9-22 and described in
Table 9-38.
Figure 9-22. IPC Generation Registers (IPCGRx)
31 4 3 1 0
SRCS27 - SRCS0 Reserved IPCG
RW +0 (per bit field) R-000 RW-0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 9-38. IPC Generation Registers Field Descriptions
Bit Field Description
31-4 SRCSx Reads return current value of internal register bit.
Writes:
• 0 = No effect
• 1 = Sets both SRCSx and the corresponding SRCCx.
3-1 Reserved Reserved
0 IPCG Reads return 0.
Writes:
• 0 = No effect
• 1 = Creates an inter-DSP/ARM interrupt.
186 Device Boot and Configuration Copyright © 2012–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: 66AK2E05 66AK2E02