66AK2E05, 66AK2E02
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
The BCx bit indicates the boot complete status of the corresponding C66x CorePac and ARM CorePac.
All BCx bits are sticky bits — that is, they can be set only once by the software after device reset and they
will be cleared to 0 on all device resets (warm reset and power-on reset).
Boot ROM code is implemented such that each C66x CorePac or ARM CorePac sets its corresponding
BCx bit immediately before branching to the predefined location in memory.
9.2.3.10 Power State Control (PWRSTATECTL) Register
The Power State Control Register (PWRSTATECTL) is controlled by the software to indicate the power-
saving mode. Under ROM code, the CorePac reads this register to differentiate between the various
power saving modes. This register is cleared only by POR and is not changed by any other device reset.
See the Hardware Design Guide for KeyStone II Devices application report (SPRABV0) for more
information. The PWRSTATECTL register is shown in Figure 9-20 and described in Table 9-36.
Figure 9-20. Power State Control Register (PWRSTATECTL)
31 3 2 1 0
Hibernation Recovery Branch Address Hibernation Mode Hibernation Standby
RW-0000 0000 0000 0000 0 RW-0 RW-0 RW-0
Legend: R = Read Only, RW = Read/Write; -n = value after reset
Table 9-36. Power State Control Register Field Descriptions
Bit Field Description
31-3 Hibernation Used to provide a start address for execution out of the hibernation modes. See the KeyStone Architecture
Recovery Branch DSP Bootloader User's Guide (SPRUGY5).
Address
2 Hibernation Mode Indicates whether the device is in hibernation mode 1 or mode 2.
• 0 = Hibernation mode 1
• 1 = Hibernation mode 2
1 Hibernation Indicates whether the device is in hibernation mode or not.
• 0 = Not in hibernation mode
• 1 = Hibernation mode
0 Standby Indicates whether the device is in standby mode or not.
• 0 = Not in standby mode
• 1 = standby mode
9.2.3.11 NMI Event Generation to C66x CorePac (NMIGRx) Register
NMIGRx registers generate NMI events to the corresponding C66x CorePac. The 66AK2Exx has has one
NMIGRx register. The NMIGR0 register generates an NMI event to C66x CorePac0. Writing a 1 to the
NMIG field generates an NMI pulse. Writing a 0 has no effect and Reads return 0 and have no other
effect. The NMI event generation to the C66x CorePac is shown in Figure 9-21 and described in Table 9-
37.
Figure 9-21. NMI Generation Register (NMIGRx)
31 1 0
Reserved NMIG
R-0000 0000 0000 0000 0000 0000 0000 000 RW-0
Legend: RW = Read/Write; -n = value after reset
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