66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
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Figure 9-15. LRESETNMI PIN Status Register (LRSTNMIPINSTAT)
31 9 8 7 1 0
Reserved NMI0 Reserved LR0
R-0 R-0 R-0 R-0
Legend: R = Read only; -n = value after reset
Table 9-31. LRESETNMI PIN Status Register Field Descriptions
Bit Field Description
31-16 Reserved
15 Reserved
14 Reserved
13 Reserved
12 Reserved
11 Reserved
10 Reserved
9 Reserved
8 NMI0 C66x CorePac0 in NMI
7 Reserved
6 Reserved
5 Reserved
4 Reserved
3 Reserved
2 Reserved
1 Reserved
0 LR0 C66x CorePac0 in Local Reset
9.2.3.6 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
The LRSTNMIPINSTAT_CLR Register clears the status of LRESET and NMI. The LRESETNMI PIN
Status Clear Register is shown in the figure and table below.
Figure 9-16. LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR)
31 9 8 7 1 0
Reserved NMI0 Reserved LR0
R-0 WC-0 R-0 WC-0
Legend: R = Read only; -n = value after reset; WC = Write 1 to Clear
Table 9-32. LRESETNMI PIN Status Clear Register Field Descriptions
Bit Field Description
31-16 Reserved
15 Reserved
14 Reserved
13 Reserved
12 Reserved
11 Reserved
10 Reserved
9 Reserved
8 NMI0 C66x CorePac0 in NMI Clear
7 Reserved
6 Reserved
182 Device Boot and Configuration Copyright © 2012–2015, Texas Instruments Incorporated
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