66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
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Table 9-26. Device Configuration Pins
CONFIGURATION PIN PIN NO. IPD/IPU
(1)
DESCRIPTION
LENDIAN
(1)(2)
V30 IPU Device endian mode (LENDIAN)
• 0 = Device operates in big endian mode
• 1 = Device operates in little endian mode
BOOTMODE[15:0]
(1)(2)
AB33, AB32, AA33, IPD Method of boot
AA30, Y32, Y30,
• See Section 9.1.2 for more details.
AB29, W33, W31,
• See the KeyStone II Architecture ARM Bootloader User's Guide
V31, W32, W30,
(SPRUHJ3) for detailed information on boot configuration.
V32, V33, Y29,
AA29
AVSIFSEL[1:0]
(1)(2)
K32, K33 IPD AVS interface selection
• 00 = AVS 4-pin 6-bit Dual-Phase VCNTL[5:2] (Default)
• 01 = AVS 4-pin 4-bit Single-Phase VCNTL[5:2]
• 10 = AVS 6-pin 6-bit Single-Phase VCNTL[5:0]
• 11 = I
2
C
MAINPLLODSEL
(1)(2)
Y33 IPD Main PLL Output divider select
• 0 = Main PLL output divider needs to be set to 2 by BOOTROM
• 1 = Reserved
BOOTMODE_RSVD
(1)
Y31 IPD Boot Mode Reserved. Secondary function for GPIO15. Pulldown
resistor required on pin.
(1) Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can be used to oppose the IPD/IPU.
For more detailed information on pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see
Section 6.4.
(2) These signal names are the secondary functions of these pins.
9.2.2 Peripheral Selection After Device Reset
Several of the peripherals on the 66AK2E0x are controlled by the Power Sleep Controller (PSC). By
default, the PCIe and HyperLink are held in reset and clock-gated. The memories in these modules are
also in a low-leakage sleep mode. Software is required to turn these memories on. Then, the software
enables the modules (turns on clocks and de-asserts reset) before these modules can be used.
If one of the above modules is used in the selected ROM boot mode, the ROM code automatically
enables the module.
All other modules come up enabled by default and there is no special software sequence to enable. For
more detailed information on the PSC usage, see the KeyStone Architecture Power Sleep Controller
(PSC) User's Guide (SPRUGV4).
9.2.3 Device State Control Registers
The 66AK2E0x device has a set of registers that are used to control the status of its peripherals. These
registers are shown in Table 9-27.
Table 9-27. Device State Control Registers
ADDRESS ADDRESS
START END SIZE ACRONYM DESCRIPTION
0x02620000 0x02620007 8B Reserved
0x02620008 0x02620017 16B Reserved
0x02620018 0x0262001B 4B JTAGID See Section 9.2.3.3
0x0262001C 0x0262001F 4B Reserved
0x02620020 0x02620023 4B DEVSTAT See Section 9.2.3.1
0x02620024 0x02620037 20B Reserved
0x02620038 0x0262003B 4B KICK0
See Section 9.2.3.4
0x0262003C 0x0262003F 4B KICK1
0x02620040 0x02620043 4B Reserved
176 Device Boot and Configuration Copyright © 2012–2015, Texas Instruments Incorporated
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