66AK2E05, 66AK2E02
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 9-23. NAND Boot Parameter Table (continued)
CONFIGURED THROUGH
BYTE OFFSET NAME DESCRIPTION BOOT CONFIGURATION PINS
24 numColumnAddrBytes Number of bytes used to specify column address NO
26 numRowAddrBytes Number of bytes used to specify row address. NO
28 numofDataBytesperPage_msw Number of data bytes in each page, MSW NO
30 numofDataBytesperPage_lsw Number of data bytes in each page, LSW NO
32 numPagesperBlock Number of Pages per Block NO
34 busWidth EMIF bus width. Only 8 or 16 bits is supported. NO
36 numSpareBytesperPage Number of spare bytes allocated per page. NO
38 csel Chip Select number (valid chip selects are 2-5) YES
40 First Block First block for RBL to try to read. YES
9.1.2.4.9 DDR3 Configuration Table
The RBL also provides an option to configure the DDR table before loading the image into the external
memory. More information on how to configure the DDR3, refer to the Bootloader User Guide. The
configuration table for DDR3 is shown in Table 9-24
Table 9-24. DDR3 Boot Parameter Table
CONFIGURED
BYTE THROUGH BOOT
OFFSET NAME DESCRIPTION CONFIGURATION PINS
0 configselect msw Selecting the configuration register below that to be set. Each NO
filed below is represented by one bit each.
4 configselect slsw Selecting the configuration register below that to be set. Each NO
filed below is represented by one bit each.
8 configselect lsw Selecting the configuration register below that to be set. Each NO
filed below is represented by one bit each.
12 pllprediv PLL pre divider value (Should be the exact value not value -1) NO
16 pllMult PLL Multiplier value (Should be the exact value not value -1) NO
20 pllPostDiv PLL post divider value (Should be the exact value not value -1) NO
24 sdRamConfig SDRAM config register NO
28 sdRamConfig2 SDRAM Config register NO
32 sdRamRefreshctl SDRAM Refresh Control Register NO
36 sdRamTiming1 SDRAM Timing 1 Register NO
40 sdRamTiming2 SDRAM Timing 2 Register NO
44 sdRamTiming3 SDRAM Timing 3 Register NO
48 IpDfrNvmTiming LP DDR2 NVM Timing Register NO
52 powerMngCtl Power management Control Register NO
56 iODFTTestLogic IODFT Test Logic Global Control Register NO
60 performcountCfg Performance Counter Config Register NO
64 performCountMstRegSel Performance Counter Master Region Select Register NO
68 readIdleCtl Read IDLE counter Register NO
72 sysVbusmIntEnSet System Interrupt Enable Set Register NO
76 sdRamOutImpdedCalcfg SDRAM Output Impedence Calibration Config Register NO
80 tempAlertCfg Temperature Alert Configuration Register NO
84 ddrPhyCtl1 DDR PHY Control Register 1 NO
88 ddrPhyCtl2 DDR PHY Control Register 1 NO
92 proClassSvceMap Priority to Class of Service mapping Register NO
96 mstId2ClsSvce1Map Master ID to Class of Service Mapping 1 Register NO
100 mstId2ClsSvce2Map Master ID to Class of Service Mapping 2Register NO
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