256K bytes
128K bytes
64K bytes
32K bytes
16K bytes
16K bytes
L2 Memory
0086 0000h
0087 0000h
0087 8000h
0087 C000h
0087 FFFFh
000 001 010 011 100
Block Base
Address
L2 Mode Bits
1/2
SRAM
4-Way
Cache
101 110
0084 0000h
0080 0000h
4-Way
Cache
4-Way
Cache
4-Way
Cache
ALL
SRAM
4-Way
Cache
4-Way
Cache
3/4
SRAM
7/8
SRAM
15/16
SRAM
31/32
SRAM
66AK2E05, 66AK2E02
www.ti.com
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Figure 4-4. L2 Memory Configurations
Global addresses that are accessible to all masters in the system are in all memory local to the
processors. In addition, local memory can be accessed directly by the associated processor through
aliased addresses, where the eight MSBs are masked to 0.
4.1.4 Multicore Shared Memory SRAM
The MSM SRAM configuration for the 66AK2E0x device is as follows:
• Memory size of 2048KB
• Can be configured as shared L2 or shared L3 memory
• Allows extension of external addresses from 2GB up to 8GB
• Has built-in memory protection features
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