66AK2E05, 66AK2E02
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
9.1.2.3.3 UART Boot Device Configuration
Figure 9-11. UART Boot Mode Configuration Field Description
DEVSTAT Boot Mode Pins ROM Mapping
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X X X X Port X X X Boot Master Sys PLL Config Min 111 Lendian
Table 9-14. UART Boot Configuration Field Descriptions
Bit Field Description
16-13 Reserved Not Used
12 Port UART Port number
• 0 = UART0
• 1 = UART1
11-9 Reserved Not Used
8 Boot Master This pin must be pulled down to GND
7-5 SYS PLL The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for
Setting the device. Table 9-25 shows settings for various input clock frequencies. (default = 4)
4 Min Minimum boot configuration select bit.
• 0 = Minimum boot pin select disabled
• 1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table
for configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
3-1 Boot Devices Boot Devices[3:1]
• 111 = UART boot mode
• Others = Other boot modes
0 Lendian Endianess
• 0 = Big endian
• 1 = Little endian
9.1.2.4 Boot Parameter Table
The ROM Bootloader (RBL) uses a set of tables to carry out the boot process. The boot parameter table is
the most common format the RBL employs to determine the boot flow. These boot parameter tables have
certain parameters common across all the boot modes, while the rest of the parameters are unique to the
boot modes. The common entries in the boot parameter table are shown in Table 9-15.
Table 9-15. Boot Parameter Table Common Parameters
BYTE OFFSET NAME DESCRIPTION
0 Length The length of the table, including the length field, in bytes.
2 Checksum The 16 bits ones complement of the ones complement of the entire table. A
value of 0 will disable checksum verification of the table by the boot ROM.
4 Boot Mode Internal values used by RBL for different boot modes.
6 Port Num Identifies the device port number to boot from, if applicable
8 SW PLL, MSW PLL configuration, MSW
10 SW PLL, LSW PLL configuration, LSW
12 Reserved Reserved
14 Reserved Reserved
16 System Freq The Frequency of the system clock in MHz
18 Core Freq The frequency of the core clock in MHz
20 Boot Master Set to TRUE if C66x is the master core.
Copyright © 2012–2015, Texas Instruments Incorporated Device Boot and Configuration 167
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