66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
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Table 9-9. NAND Boot Device Configuration Field Descriptions (continued)
Bit Field Description
7-5 SYS PLL Setting The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock
setting for the device. Table 9-25 shows settings for various input clock frequencies.
4 Min Minimum boot pin select. When Min is 1, it means that the BOOTMODE [15:3] pins are don't cares. Only
BOOTMODE [2:0] pins (DEVSTAT[3:1]) will determine boot. Default values are assigned to values that
would normally be set by the other BOOTMODE pins when Min is 0.
• 0 = Minimum boot pin select disabled
• 1 = Minimum boot pin select enabled.
3-1 Boot Devices Boot Devices
• 011 = NAND boot mode
• Others = Other boot modes
0 Lendian Endianess
• 0 = Big endian
• 1 = Little endian
9.1.2.3 Ethernet (SGMII) Boot Device Configuration
Figure 9-8. Ethernet (SGMII) Boot Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NETCP Lane
Ref Clock Ext Con X Boot Master Sys PLL Cfg Min 101 Lendian
clk Setup
Table 9-10. Ethernet (SGMII) Boot Device Configuration Field Descriptions
Bit Field Description
16 NETCP clk NETCP clock reference
• 0 = NETCP clocked at the same reference as the core reference
• 1 = NETCP clocked at the same reference as the SerDes reference (default)
15-14 Ref Clock Reference clock frequency
• 0 = 125MHz
• 1 = 156.25MHz (default)
• 2 = Reserved
• 3 = Reserved
13-12 Ext Con External connection mode
• 0 = MAC to MAC connection, master with auto negotiation
• 1 = MAC to MAC connection, slave with auto negotiation (default)
• 2 = MAC to MAC, forced link, maximum speed
• 3 = MAC to fiber connection
11-9 Lane Setup Lane Setup.
• 0 = All SGMII ports enabled (default)
• 1 = Only SGMII port 0 enabled
• 2 = SGMII port 0 and 1 enabled
• 3 = SGMII port 0, 1 and 2 enabled
• 4-5 = Reserved
8 Boot Master This pin must be pulled down to GND
7-5 SYS PLL Setting The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock
setting for the device. Default system reference clock is 156.25 MHz. Table 9-25 shows settings for
various input clock frequencies. (default = 4)
164 Device Boot and Configuration Copyright © 2012–2015, Texas Instruments Incorporated
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