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66AK2E05XABD4

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型号: 66AK2E05XABD4
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功能描述: 66AK2E0x Multicore DSPARM KeyStone II System-on-Chip (SoC)
PDF文件大小: 1546.9 Kbytes
PDF页数: 共282页
制造商: TI[Texas Instruments]
制造商LOGO: TI[Texas Instruments] LOGO
制造商网址: http://www.ti.com
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120%
L1D Memory
00F0 0000h
00F0 4000h
00F0 6000h
00F0 7000h
00F0 8000h
1/2
SRAM
2-Way
Cache
3/4
SRAM
7/8
SRAM
All
SRAM
000 001 010 011 100
Block Base
Address
L1D Mode Bits
4K bytes
8K bytes
16K bytes
4K bytes
2-Way
Cache
2-Way
Cache
2-Way
Cache
66AK2E05, 66AK2E02
SPRS865D NOVEMBER 2012REVISED MARCH 2015
www.ti.com
Figure 4-3. L1D Memory Configurations
4.1.3 L2 Memory
The L2 memory configuration for the 66AK2E0x device is as follows:
Total memory size is 512KB
Each CorePac contains 512KB of memory
Local starting address for each CorePac is 0080 0000h
L2 memory can be configured as all SRAM, all 4-way set-associative cache, or a mix of the two. The
amount of L2 memory that is configured as cache is controlled through the L2MODE field of the L2
Configuration Register (L2CFG) of the C66x CorePac. Figure 4-4 shows the available SRAM/cache
configurations for L2. By default, L2 is configured as all SRAM after device reset.
16 C66x CorePac Copyright © 2012–2015, Texas Instruments Incorporated
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Product Folder Links: 66AK2E05 66AK2E02
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