66AK2E05, 66AK2E02
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 9-4. Sleep Boot Configuration Field Descriptions (continued)
Bit Field Description
12 PLLEN Enable the System PLL
• 0 = PLL disabled (default)
• 1 = PLL enabled
11-9 Reserved Reserved
8 Boot Master This pin must be pulled down to GND
7-5 SYS PLL The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for
Setting the device. Table 9-25 shows settings for various input clock frequencies.
4 Min Minimum boot configuration select bit.
• 0 = Minimum boot pin select disabled
• 1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table
for configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
3-1 Boot Devices Boot Devices[3:1] used in conjunction with Boot Device [14]
• 000 = Sleep
• Others = Other boot modes
0 Lendian Endianess (device)
• 0 = Big endian
• 1 = Little endian
9.1.2.2.2 I
2
C Boot Device Configuration
9.1.2.2.2.1 I
2
C Passive Mode
In passive mode, the device does not drive the clock, but simply acks data received on the specified
address.
Figure 9-3. I
2
C Passive Mode Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Boot
Slave Addr 1 Port X Sys PLL Config Min 000 Lendian
Master
Table 9-5. I
2
C Passive Mode Device Configuration Field Descriptions
Bit Field Description
16-15 Slave Addr I
2
C Slave boot bus address
• 0 = I
2
C slave boot bus address is 0x00
• 1 = I
2
C slave boot bus address is 0x10 (default)
• 2 = I
2
C slave boot bus address is 0x20
• 3 = I
2
C slave boot bus address is 0x30
14 Boot Devices Boot Device[14] used in conjunction with Boot Devices [Use din conjunction with bits 3-1]
• 0 = Other boot modes
• 1= I
2
C Slave boot mode
13-12 Port I
2
C port number
• 0 = I
2
C0
• 1 = I
2
C1
• 2 = I
2
C2
• 3 = Reserved
11-9 Reserved Reserved
8 Boot Master This pin must be pulled down to GND
7-5 SYS PLL The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for
Setting the device. Table 9-25 shows settings for various input clock frequencies.
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