66AK2E05, 66AK2E02
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 9-2. ARM Boot RAM Memory Map (continued)
START ADDRESS SIZE DESCRIPTION
0xc1b_8500 0x100 Boot Parameter Tables, Core 3
0xc1b_8600 0x19e0 Boot Data, Core 3
0xc1b_9fe0 0x1010 Boot Trace, Core 3
0xc1c_0000 0x4_0000 Secure MSMC
9.1.2 Boot Modes Supported
The C66x Boot Master modes are not supported only the ARM CorePac Boot Master modes are. The
device supports several boot processes, which leverage the internal boot ROM. Most boot processes are
software-driven, using the BOOTMODE[15:0] device configuration inputs to determine the software
configuration that must be completed. From a hardware perspective, there are two possible boot modes:
• Public ROM Boot when the ARM CorePac Core0 is the boot master — In this boot mode, the ARM
CorePac performs the boot process while the C66x CorePacs execute idle instructions. When the ARM
CorePac Core0 finishes the boot process, it may send interrupts to the C66x CorePacs and Cortex-
A15 processor cores through IPC registers. The C66x CorePacs complete the boot management
operations and begin executing from the predefined locations.
• Secure ROM Boot when the ARM CorePac0 is the boot master — The C66x CorePac0 and the
ARM CorePac Core0 are released from reset simultaneously and begin executing from secure ROM.
The ARM CorePac Core0 initiates the boot process. The C66x CorePac0 performs any authentication
and decryption required on the bootloaded image for the C66x CorePacs and ARM CorePac prior to
beginning execution. For more information, refer to the Secure device Addendum.
The boot process performed by the ARM CorePac Core0 in public ROM boot and secure ROM boot are
determined by the BOOTMODE[15:0] value in the DEVSTAT register. The ARM CorePac Core0 read this
value, and then execute the associated boot process in software. The figure below shows the bits
associated with BOOTMODE[15:0] pins (DEVSTAT[16:1] register bits) when the ARM CorePac is the boot
master. Note that Figure 9-1 does not include bit 0 of the DEVSTAT contents. Bit 0 is used to select
overall system endianess that is independent of the boot mode.
The boot ROM will continue attempting to boot in this mode until successful or an unrecoverable error
occurs.
The PLL settings are shown at the end of this section, and the PLL set-up details can be found in
Section 11.5.
NOTE
It is important to keep in mind that BOOTMODE[15:0] pins map to DEVSTAT[16:1] bits of
the DEVSTAT register.
Copyright © 2012–2015, Texas Instruments Incorporated Device Boot and Configuration 157
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